Cristiana Bolchini

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International and National Conferences with peer review

1. C. Bolchini and A. Miele, "An Application-Level Dependability Analysis Framework for Embedded Systems," in Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, pp. 171-178, October 2011 bibtex

   @inproceedings{DFT2011.BM,
    author = {Cristiana Bolchini and Antonio Miele},
   title = {An Application-Level Dependability Analysis Framework for Embedded Systems},
   booktitle = {Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT},
   year = {2011},
   month = {October},
   pages = {171-178},
   doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2011.25} 
   }  
   

2. C. Bolchini and C. Sandionigi, "A reliability-aware partitioner for multi-FPGA platforms," in Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, pp. 34-40, October 2011 bibtex

   @inproceedings{DFT2011.BS,
    author = {Cristiana Bolchini and Chiara Sandionigi},
   title = {A reliability-aware partitioner for multi-FPGA platforms},
   booktitle = {Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT},
   year = {2011},
   month = {October},
   pages = {34-40},
   doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2011.20} 
   }  
   

3. L. Amati, C. Bolchini and F. Salice, "Optimal Test Set Selection for Fault Diagnosis Improvement," in Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, pp. 93-99, October 2011 bibtex

   @inproceedings{DFT2011.ABS,
    author = {Luca Amati and Cristiana Bolchini and Fabio Salice},
   title = {Optimal Test Set Selection for Fault Diagnosis Improvement},
   booktitle = {Proc. IEEE Intl Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT},
   year = {2011},
   month = {October},
   pages = {93-99},
   doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2011.57} 
   }   
   

4. C. Bolchini, A. Miele and C. Sandionigi, "Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems," in Proc. IEEE Int. Conf. Field Programmable Logic and Applications, pp. 532-538, September 2011 bibtex

   @inproceedings{FPL2011,
    author = {Cristiana Bolchini and Antonio Miele and Chiara Sandionigi},
   title = {Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems},
   booktitle = {Proc. IEEE Int. Conf. Field Programmable Logic and Applications},
   year = {2011},
   month = {September},
   pages = {532-538},
   doi = {http://doi.ieeecomputersociety.org/10.1109/FPL.2011.104} 
   }  
   

5. C. Bolchini, C. Sandionigi, L. Fossati and D. Merodio Codinachs, "A reliable fault classifier for dependable systems on SRAM-based FPGAs," in Proc. IEEE Int. On-Line Testing Symposium, IOLTS, pp. 92-97, July 2011 bibtex

   @inproceedings{IOLTS2011,
    author = {Cristiana Bolchini and Chiara Sandionigi and L. Fossati and D. Merodio Codinachs},
   title = {A reliable fault classifier for dependable systems on SRAM-based FPGAs},
   booktitle = {Proc. IEEE Int. On-Line Testing Symposium, IOLTS},
   year = {2011},
   pages = {92-97},
   month = {July,} doi = {http://doi.ieeecomputersociety.org/10.1109/IOLTS.2011.5993817} 
   }  
   

6. C. Bolchini, A. Miele and C. Pilato, "Combined architecture and hardening techniques exploration for reliable embedded system design," in Proc. ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 301-306, May 2011 bibtex pdf 

   @inproceedings{GLSVLSI2011.BMP,
    Author = {Cristiana Bolchini and Antonio Miele and Christian Pilato},
   Booktitle = {Proc. ACM Great Lakes Symposium on VLSI, GLSVLSI},
   Doi = {http://doi.acm.org/10.1145/1973009.1973069},
   Month = {May},
   Pages = {301-306},
   Title = {Combined architecture and hardening techniques exploration for reliable embedded system design},
   Year = {2011},
   }  
   

7. L. Amati, C. Bolchini and F. Salice, "Test Selection Policies for Faster Incremental Fault Detection," in Proc. IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems, DFT, pp. 310-318, Oct 2010 bibtex

   @inproceedings{DFT2010c,
    Author = {Luca Amati and Cristiana Bolchini and Fabio Salice},
   Booktitle = {Proc. IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems, DFT},
   Doi = {http://dx.doi.org/10.1109/DFT.2010.45},
   Keywords = {Incremental Functional Diagnosis, Test Set},
   Month = {Oct},
   Pages = {310-318},
   Title = {Test Selection Policies for Faster Incremental Fault Detection},
   Year = {2010},
   }  
   

8. C. Bolchini, L. Fossati, D. Merodio Codinachs, A. Miele and C. Sandionigi, "A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA platforms," in Proc. IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems, DFT, pp. 191-199, Oct 2010 bibtex

   @inproceedings{DFT2010b,
    Author = {Cristiana Bolchini and L. Fossati and D. Merodio Codinachs and Antonio Miele and Chiara Sandionigi},
   Booktitle = {Proc. IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems, DFT},
   Doi = {http://dx.doi.org/10.1109/DFT.2010.30},
   Keywords = {Multi-FPGA, Reconfiguration Controller, Fault Tolerance},
   Month = {Oct},
   Pages = {191-199},
   Title = {A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA platforms},
   Year = {2010},
   }  
   

9. C. Bolchini and A. Miele, "Reliability-Driven System-Level Synthesis of Embedded Systems," in Proc. IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems, DFT, pp. 35-43, Oct 2010 bibtex

   @inproceedings{DFT2010a,
    Author = {Cristiana Bolchini and Antonio Miele},
   Booktitle = {Proc. IEEE Intl Symp on Defect and Fault Tolerance in VLSI Systems, DFT},
   Doi = {http://dx.doi.org/10.1109/DFT.2010.11},
   Keywords = {System-Level Synthesis, Reliability-Aware},
   Month = {Oct},
   Pages = {35-43},
   Title = {Reliability-Driven System-Level Synthesis of Embedded Systems},
   Year = {2010},
   }  
   

10. L. Amati, C. Bolchini, F. Salice and F. Franzoso, "Improving Fault Diagnosis Accuracy by Automatic Test Set Modification," in Proc. IEEE Int. Test Conference, November 2010 bibtex

    @inproceedings{ITC2010,
     Author = {Luca Amati and Cristiana Bolchini and Fabio Salice and F. Franzoso},
    Booktitle = {Proc. IEEE Int. Test Conference},
    Doi = {http://dx.doi.org/10.1109/TEST.2010.5699250},
    Keywords = {Incremental Functional Diagnosis, Test Set},
    Month = {November},
    Title = {Improving Fault Diagnosis Accuracy by Automatic Test Set Modification},
    Year = {2010},
    }  
    

11. L. Amati, C. Bolchini, F. Salice and F. Franzoso, "A Formal Condition to Stop an Incremental Automatic Functional Diagnosis," in Proc. 13th EUROMICRO Conf. Digital System Design - Architectures, Methods and Tools, pp. 637-643, Sep 2010 bibtex

    @inproceedings{DSD2010,
     Author = {Luca Amati and Cristiana Bolchini and Fabio Salice and Federico Franzoso},
    Booktitle = {Proc. 13th EUROMICRO Conf. Digital System Design - Architectures, Methods and Tools},
    Doi = {http://dx.doi.org/10.1109/DSD.2010.98},
    Keywords = {Diagnosis, Incremental Functional Diagnosis, Stop, Faulty Candidate},
    Month = {Sep},
    Pages = {637-643},
    Title = {A Formal Condition to Stop an Incremental Automatic Functional Diagnosis},
    Year = {2010},
    }  
    

12. C. Bolchini, P. Luca Lanzi and A. Miele, "A Multi-Objective Genetic Algorithm Framework for Design Space Exploration of Reliable FPGA based Systems," in Proc. IEEE World Congress on Computational Intelligence, CEC, pp. 419-426, July 2010 bibtex

    @inproceedings{CEC2010,
     Author = {Cristiana Bolchini and Pier Luca Lanzi and Antonio Miele},
    Booktitle = {Proc. IEEE World Congress on Computational Intelligence, CEC},
    Doi = {http://dx.doi.org/10.1109/CEC.2010.5586376},
    Keywords = {Design Space Exploration, FPGA},
    Month = {July},
    Pages = {419-426},
    Title = {A Multi-Objective Genetic Algorithm Framework for Design Space Exploration of Reliable FPGA based Systems},
    Year = {2010},
    }  
    

13. A. Miele, C. Bolchini, C. Sandionigi, N. Battezzati, L. Sterpone and M. Violante, "An integrated flow for the design of hardened circuits on SRAM-based FPGAs," in Proc. IEEE European Test Symposium, pp. 214-219, May 2010 bibtex

    @inproceedings{ETS2010,
     Author = {Antonio Miele and Cristiana Bolchini and Chiara Sandionigi and N. Battezzati and L. Sterpone and M. Violante},
    Booktitle = {Proc. IEEE European Test Symposium},
    Doi = {http://dx.doi.org/10.1109/ETSYM.2010.5512757},
    Keywords = {Reconfiguration, SRAM-based FPGAs, R4R},
    Month = {May},
    Pages = {214-219},
    Title = {An integrated flow for the design of hardened circuits on SRAM-based FPGAs},
    Year = {2010},
    }  
    

14. C. Bolchini, F. Castro and A. Miele, "A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-based FPGA Systems," in Proc. IEEE Intl Symp on Defect and Fault Tolerance of of VLSI Systems, pp. 173-181, Oct 2009 bibtex

    @inproceedings{DFT2009a,
     Author = {Cristiana Bolchini and F. Castro and Antonio Miele},
    Booktitle = {Proc. IEEE Intl Symp on Defect and Fault Tolerance of of VLSI Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2009.10},
    Keywords = {Fault injection, SRAM-based FPGAs},
    Month = {Oct},
    Pages = {173-181},
    Title = {A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-based FPGA Systems},
    Year = {2009},
    }  
    

15. L. Amati, C. Bolchini, L. Frigerio, F. Salice, B. Eklow, A. Suvatne, E. Brambilla, F. Franzoso and M. Martin, "An incremental approach to functional diagnosis," in Proc. IEEE Intl Symp on Defect and Fault Tolerance of of VLSI Systems, pp. 392-400, Oct 2009 bibtex

    @inproceedings{DFT2009b,
     Author = {Luca Amati and Cristiana Bolchini and L. Frigerio and Fabio Salice and B. Eklow and A. Suvatne and E. Brambilla and F. Franzoso and M. Martin},
    Booktitle = {Proc. IEEE Intl Symp on Defect and Fault Tolerance of of VLSI Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2009.29},
    Keywords = {Diagnosis},
    Month = {Oct},
    Pages = {392-400},
    Title = {An incremental approach to functional diagnosis},
    Year = {2009},
    }  
    

16. G. Beltrame, C. Bolchini and A. Miele, "Multi-level fault modeling for transaction-level specifications," in Proc. ACM 19th Great Lake Symposium on VLSI, pp. 87-92, May 2009 bibtex

    @inproceedings{GLSVLSI2009,
     Author = {Giovanni Beltrame and Cristiana Bolchini and Antonio Miele},
    Booktitle = {Proc. ACM 19th Great Lake Symposium on VLSI},
    Doi = {http://doi.acm.org/10.1145/1531542.1531565},
    Keywords = {Fault Models, SystemC},
    Month = {May},
    Pages = {87-92},
    Title = {Multi-level fault modeling for transaction-level specifications},
    Year = {2009},
    }  
    

17. C. Bolchini and A. Miele, "Design Space Exploration for the Design of Reliable SRAM-based FPGA Systems," in Proc. IEEE Intl Symp on Defect and Fault Tolerance of of VLSI Systems, pp. 332-340, Oct 2008 bibtex

    @inproceedings{DFT2008,
     Author = {Cristiana Bolchini and Antonio Miele},
    Booktitle = {Proc. IEEE Intl Symp on Defect and Fault Tolerance of of VLSI Systems},
    Doi = {http://dx.doi.org/10.1109/DFT.2008.8},
    Keywords = {SRAM-based FPGA, Genetic Algorithms, Design Space Exploration},
    Month = {Oct},
    Pages = {332-340},
    Read = {Yes},
    Title = {Design Space Exploration for the Design of Reliable SRAM-based FPGA Systems},
    Year = {2008},
    }  
    

18. C. Bolchini, A. Miele and D. Sciuto, "Fault Models and Injection Strategies in SystemC Specifications," in 11th EUROMICRO Conf. on Digital System Design - Architectures, Methods and Tools, pp. 88-95, Sep 2008 bibtex

    @inproceedings{DSD2008,
     Author = {Cristiana Bolchini and Antonio Miele and Donatella Sciuto},
    Booktitle = {11th EUROMICRO Conf. on Digital System Design - Architectures, Methods and Tools},
    Doi = {http://dx.doi.org/10.1109/DSD.2008.35},
    Keywords = {Fault Models, Fault Injection, ReSP},
    Month = {Sep},
    Pages = {88-95},
    Read = {Yes},
    Title = {Fault Models and Injection Strategies in SystemC Specifications},
    Year = {2008},
    }  
    

19. C. Bolchini, A. Miele and D. Sciuto, "Fault Models and Injection Strategies for a Reflective Simulation Platform," in Poster Presentation at IEEE European Test Symposium, May 2008 bibtex

    @inproceedings{ETS2008,
     Author = {Cristiana Bolchini and Antonio Miele and Donatella Sciuto},
    Booktitle = {Poster Presentation at IEEE European Test Symposium},
    Keywords = {Fault Models, SystemC, Fault Injection},
    Month = {May},
    Title = {Fault Models and Injection Strategies for a Reflective Simulation Platform},
    Year = {2008}
    }  
    

20. G. Beltrame, C. Bolchini, L. Fossati, A. Miele and D. Sciuto, "ReSP: A Non-Intrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration," in Proc. IEEE 13th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 673-678, Jan 2008 bibtex

    @inproceedings{ASPDAC2008,
     Annote = {Best Paper Candidate},
    Author = {Giovanni Beltrame and Cristiana Bolchini and Luca Fossati and Antonio Miele and Donatella Sciuto},
    Booktitle = {Proc. IEEE 13th Asia and South Pacific Design Automation Conference (ASP-DAC)},
    Keywords = {ReSP, Fault Injection},
    Month = {Jan},
    Pages = {673-678},
    Title = {{ReSP}: A Non-Intrusive Transaction-Level Reflective {MPSoC} Simulation Platform for Design Space Exploration},
    Year = {2008}
    }  
    

21. E. Team, "Emergent Semantics and Cooperation in Multi-Knowledge Environments: the ESTEEM Architecture," in VLDB Intl Workshop on Semantic Data and Service Integration, pp. 1-12, 2007 bibtex

    @inproceedings{SDSI2007,
     Author = {Esteem Team},
    Booktitle = {VLDB Intl Workshop on Semantic Data and Service Integration},
    Pages = {1-12},
    Title = {Emergent Semantics and Cooperation in Multi-Knowledge Environments: the ESTEEM Architecture},
    Year = {2007}
    }  
    

22. C. Bolchini, E. Quintarelli and R. Rossato, "Relational data tailoring through view composition," in Proc. 26th International Conference on Conceptual Modeling, vol. 4801 LNCS, pp. 149-164, 2007 bibtex

    @inproceedings{ER2007,
     Author = {Cristiana Bolchini and Elisa Quintarelli and Rosalba Rossato},
    Booktitle = {Proc. 26th International Conference on Conceptual Modeling},
    Doi = {http://dx.doi.org/10.1007/978-3-540-75563-0_12},
    Keywords = {Relational Data Tailoring, Relational Operators},
    Pages = {149-164},
    Title = {Relational data tailoring through view composition},
    Volume = {4801 LNCS},
    Year = {2007},
    }  
    

23. C. Bolchini, E. Quintarelli, R. Rossato and L. Tanca, "Using context for the extraction of relational views," in Proc. 6th Intl and Interdisciplinary Conf. Modeling and Using Context, vol. 4635 LNAI, pp. 108-121, 2007 bibtex

    @inproceedings{CONTEXT2007,
     Author = {Cristiana Bolchini and Elisa Quintarelli and Rosalba Rossato and Letizia Tanca},
    Booktitle = {Proc. 6th Intl and Interdisciplinary Conf. Modeling and Using Context},
    Doi = {http://dx.doi.org/10.1007/978-3-540-74255-5_9},
    Keywords = {Context-ADDICT, Relational Operators, Relational Data Tailoring},
    Pages = {108-121},
    Title = {Using context for the extraction of relational views},
    Volume = {4635 LNAI},
    Year = {2007},
    }  
    

24. C. Bolchini, C. A. Curino, G. Orsi, E. Quintarelli, R. Rossato, F. A. Schreiber and L. Tanca, "Context-aware views for mobile users," in Proc. 10th DELOS Thematic Workshop on Personalized Access, Profile Management, and Context Awareness in Digital Libraries, pp. 1-5, 2007 bibtex

    @inproceedings{PERSDL2007,
     Author = {Cristiana Bolchini and Carlo A. Curino and Giorgio Orsi and Elisa Quintarelli and Rosalba Rossato and Fabio A. Schreiber and Letizia Tanca},
    Booktitle = {Proc. 10th DELOS Thematic Workshop on Personalized Access, Profile Management, and Context Awareness in Digital Libraries},
    Pages = {1-5},
    Title = {Context-aware views for mobile users},
    Year = {2007}
    }  
    

25. C. Bolchini, A. Miele and M. D. Santambrogio, "TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs," in Proc. 22nd IEEE Intl Symp. on Defect and Fault-Tolerance in VLSI Systems, pp. 87-95, Sep 2007 bibtex

    @inproceedings{DFT2007r4r,
     Author = {Cristiana Bolchini and Antonio Miele and Marco D. Santambrogio},
    Booktitle = {Proc. 22nd IEEE Intl Symp. on Defect and Fault-Tolerance in VLSI Systems},
    Doi = {http://dx.doi.org/10.1109/DFT.2007.25},
    Keywords = {Dynamic Partial Reconfiguration, FPGA, Fault Tolerance},
    Month = {Sep},
    Pages = {87-95},
    Title = {{TMR} and Partial Dynamic Reconfiguration to mitigate {SEU} faults in {FPGAs}},
    Year = {2007},
    }  
    

26. G. Beltrame, C. Bolchini, L. Fossati, A. Miele and D. Sciuto, "A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip," in Proc. 22nd IEEE Intl Symp. on Defect and Fault-Tolerance in VLSI Systems, pp. 132--140, Sep 2007 bibtex

    @inproceedings{DFT2007hwsw,
     Author = {Giovanni Beltrame and Cristiana Bolchini and Luca Fossati and Antonio Miele and Donatella Sciuto},
    Booktitle = {Proc. 22nd IEEE Intl Symp. on Defect and Fault-Tolerance in VLSI Systems},
    Doi = {http://dx.doi.org/10.1109/DFT.2007.35},
    Keywords = {ResP, HW/SW CO-Design, Fault Injection},
    Month = {Sep},
    Pages = {132--140},
    Title = {A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip},
    Year = {2007},
    }  
    

27. C. Bolchini, F. Salice and M. D. Santambrogio, "Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs," in Proc. Intl. Conf. of Engineering of Reconfigurable Systems and Algorithms (ERSA), 2007 bibtex

    @inproceedings{ERSA2007,
     Author = {Cristiana Bolchini and Fabio Salice and Marco D. Santambrogio},
    Booktitle = {Proc. Intl. Conf. of Engineering of Reconfigurable Systems and Algorithms (ERSA)},
    Keywords = {FPGA, Dynamic Partial Reconfiguration},
    Title = {{Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs}},
    Year = {2007}
    }  
    

28. C. Bolchini, C. Brandolese, L. Frigerio, V. Rana, F. Salice and M. D. Santambrogio, "RoadRunner and IPGen: a combined solution to speedup configurable systems design," in Proc. Designer Forum 3rd Southern Conference on Programmable Logic (SPL), 2007 bibtex

    @inproceedings{SPL2007,
     Author = {Cristiana Bolchini and Carlo Brandolese and Laura Frigerio and Vincenzo Rana and Fabio Salice and Marco D. Santambrogio},
    Booktitle = {Proc. Designer Forum 3rd Southern Conference on Programmable Logic (SPL)},
    Keywords = {RoadRunner},
    Title = {RoadRunner and IPGen: a combined solution to speedup configurable systems design},
    Year = {2007}
    }  
    

29. C. Bolchini, C. A. Curino, G. Orsi, E. Quintarelli, F. A. Schreiber and L. Tanca, "CADD: a tool for context modeling and data tailoring," in Proc. IEEE 8th Int. Conf. on Mobile Data Management, MDM, pp. 221-223, 2007 bibtex

    @inproceedings{MDM2007,
     Author = {Cristiana Bolchini and Carlo A. Curino and Giorgio Orsi and Elisa Quintarelli and Fabio A. Schreiber and Letizia Tanca},
    Booktitle = {Proc. IEEE 8th Int. Conf. on Mobile Data Management, MDM},
    Doi = {http://dx.doi.org/10.1109/MDM.2007.42},
    Keywords = {Context-ADDICT},
    Pages = {221-223},
    Title = {{CADD}: a tool for context modeling and data tailoring},
    Year = {2007},
    }  
    

30. C. Bolchini, D. Quarta and M. Santambrogio, "SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration," in Proc. ACM/IEEE 17th Great Lake Symposium on VLSI, pp. 55-60, March 2007 bibtex

    @inproceedings{GLSVLSI2007,
     Author = {Cristiana Bolchini and Davide Quarta and Marco Santambrogio},
    Booktitle = {Proc. ACM/IEEE 17th Great Lake Symposium on VLSI},
    Doi = {http://doi.acm.org/10.1145/1228784.1228803},
    Keywords = {FPGA, Dynamic Partial Reconfiguration, Fault Detection, SEU},
    Location = {Stresa, Italy},
    Month = {March},
    Pages = {55-60},
    Title = {{SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration}},
    Year = {2007},
    }  
    

31. C. Bolchini, C. A. Curino, F. Alberto Schreiber and L. Tanca, "Context integration for mobile data tailoring," in Proc. ACM/IEEE Mobile Data Management, pp. 5.1-5.8, 2006 bibtex

    @inproceedings{MDM2006,
     Author = {Cristiana Bolchini and Carlo A. Curino and Fabio Alberto Schreiber and Letizia Tanca},
    Booktitle = {Proc. ACM/IEEE Mobile Data Management},
    Doi = {http://dx.doi.org/10.1109/MDM.2006.52},
    Keywords = {Context-ADDICT, Mobile},
    Pages = {5.1-5.8},
    Title = {Context integration for mobile data tailoring},
    Year = {2006},
    }  
    

32. C. Bolchini and E. Quintarelli, "Filtering mobile data by means of context: a methodology," in Proc. ECAI Workshops - Int. Workshop on Context Representation and Reasoning (CRR), pp. 13-18, August 2006 bibtex

    @inproceedings{CRR2006,
     Abstract = {The goal of this paper is the introduction of a methodology for designing context-aware data selection for portable devices, where computation, memory, power and connectivity resources are limited, and thus, the possibility to tailor the available, usually too rich, data according to context is a mandatory task. First of all, we will introduce the concept of context and its model, a data structure that expresses knowledge on the user, the environment and the possible scenarios. We will then focus on the proposed methodology for selecting, by means of such information, the relevant data to be made available on a user device. An overall picture of the complete scenario for this context-aware data design and tailoring system will be also provided},
    Author = {Cristiana Bolchini and Elisa Quintarelli},
    Booktitle = {Proc. ECAI Workshops - Int. Workshop on Context Representation and Reasoning (CRR)},
    Keywords = {Context-ADDICT, Context Dimension Tree, Data Views Design, XML},
    Location = {Riva del Garda, I},
    Month = {August},
    Pages = {13-18},
    Title = {Filtering mobile data by means of context: a methodology},
    Year = {2006}
    }  
    

33. C. Bolchini and E. Quintarelli, "Context-Driven Data Filtering: A Methodology," in Proc. OTM Workshops - Int. Workshop on Context-Aware Mobile Systems (CAMS), pp. 1986-1995, October 2006 bibtex

    @inproceedings{CAMS2006,
     Abstract = {The goal of this paper is the introduction of a methodology for designing context-driven data selection, that is the possibility to tailor the available, usually too rich, data to be held on portable mobile devices, according to context. First of all, we will introduce the concept of context and its model, a data structure that expresses knowledge on the user, the environment and the possible scenarios. We will then focus on the proposed methodology for selecting, by means of such information, the relevant data to be made available on a user device. The proposed methodology can be adopted to select data of interest for portable devices, where computation, memory, power and connectivity resources are limited, and thus, tailororing the available, usually too rich, data according to context is a mandatory task},
    Author = {Cristiana Bolchini and Elisa Quintarelli},
    Booktitle = {Proc. OTM Workshops - Int. Workshop on Context-Aware Mobile Systems (CAMS)},
    Doi = {http://dx.doi.org/10.1007/11915072_107},
    Editor = {R. Meersman, Z. Tari, P. Herrero et al},
    Keywords = {Context-ADDICT, XML, Data filtering methodology},
    Location = {Montpellier, F},
    Month = {October},
    Pages = {1986-1995},
    Publisher = {Springer Berlin / Heidelberg},
    Rss-Description = {Introduction of a methodology for designing context-driven data selection, that is the possibility to tailor the available, usually too rich, data to be held on portable mobile devices, according to context},
    Series = {LNCS 4278},
    Title = {Context-Driven Data Filtering: A Methodology},
    Year = {2006},
    }  
    

34. C. Bolchini, A. Miele, M. Rebaudengo, D. Sciuto, L. Sterpone and M. Violante, "Combined software and hardware techniques for the design of reliable IP processors," in Proc. IEEE Defect and Fault Tolerance in VLSI Systems Symposium, DFT, pp. 265 - 273, October 2006 bibtex

    @inproceedings{DFT2006,
     Author = {Cristiana Bolchini and Antonio Miele and Maurizio Rebaudengo and Donatella Sciuto and Luca Sterpone and Massimo Violante},
    Booktitle = {Proc. IEEE Defect and Fault Tolerance in VLSI Systems Symposium, DFT},
    Doi = {http://dx.doi.org/10.1109/DFT.2006.18},
    Keywords = {Software Techniques, SEU, Fault Detection, IP Processors},
    Location = {Arlington, VA, USA},
    Month = {October},
    Pages = {265 - 273},
    Publisher = {IEEE Computer Society},
    Title = {Combined software and hardware techniques for the design of reliable {IP} processors},
    Year = {2006},
    }  
    

35. C. Bolchini, P. Ferrandi, P. Luca Lanzi and F. Salice, "Toward an FPGA Implementation of XCS," in , pp. 2053-2060, 2005 bibtex

    @inproceedings{CEC2005,
     Author = {Cristiana Bolchini and Paolo Ferrandi and Pier Luca Lanzi and Fabio Salice},
    Doi = {http://dx.doi.org/10.1109/CEC.2005.1554948},
    Keywords = {XCS, FPGA},
    Pages = {2053-2060},
    Title = {Toward an FPGA Implementation of XCS},
    Year = {2005},
    }  
    

36. C. Bolchini, L. Pomante, F. Salice and D. Sciuto, "Reliable System Specification for Self-Checking Data-Paths," in Proc. IEEE Conf. Design, Automation and Test in Europe, pp. 1278-1283, 2005 bibtex

    @inproceedings{DATE2005,
     Author = {Cristiana Bolchini and Luigi Pomante and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Conf. Design, Automation and Test in Europe},
    Doi = {http://dx.doi.org/10.1109/DATE.2005.259},
    Keywords = {Self-Checking Circuits, Data Path},
    Pages = {1278-1283},
    Title = {Reliable System Specification for Self-Checking Data-Paths},
    Year = {2005},
    }  
    

37. C. Bolchini, A. Miele, F. Salice and D. Sciuto, "A model of soft error effects in generic IP processors," in Proc. IEEE Defect and Fault Tolerance in VLSI Systems Symposium, pp. 334-342, October 2005 bibtex

    @inproceedings{DFT2005,
     Author = {Cristiana Bolchini and Antonio Miele and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Defect and Fault Tolerance in VLSI Systems Symposium},
    Doi = {10.1109/DFTVS.2005.10},
    Keywords = {IP Processors, SEU, Fault-Error Classification, Software Techniques},
    Location = {Monterey, CA, USA},
    Month = {October},
    Pages = {334-342},
    Title = {A model of soft error effects in generic IP processors},
    Year = {2005},
    }  
    

38. C. Bolchini, A. Miele, F. Salice and D. Sciuto, "Reliable System Co-Design: the FIR Case Study," in Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems, pp. 433-441, 2004 bibtex

    @inproceedings{DFT2004,
     Author = {Cristiana Bolchini and Antonio Miele and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems},
    Doi = {http://dx.doi.org/10.1109/DFTVS.2004.1347868},
    Pages = {433-441},
    Title = {Reliable System Co-Design: the FIR Case Study},
    Year = {2004},
    }  
    

39. C. Bolchini, L. Pomante, F. Salice, D. Sciuto and R. Zavaglia, "An Integrated Design Approach for Self-Checking FPGAs," in Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems, pp. 443-450, 2003 bibtex

    @inproceedings{DFT2003,
     Author = {Cristiana Bolchini and Luigi Pomante and Fabio Salice and Donatella Sciuto and R. Zavaglia},
    Booktitle = {Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250142},
    Pages = {443-450},
    Title = {An Integrated Design Approach for Self-Checking FPGAs},
    Year = {2003},
    }  
    

40. C. Bolchini, L. Pomante, F. Salice and D. Sciuto, "A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems," in Proc. IEEE Intl On-Line Testing Workshop, pp. 32-36, 2002 bibtex

    @inproceedings{IOLTW2002,
     Author = {Cristiana Bolchini and Luigi Pomante and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Intl On-Line Testing Workshop},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2002.1030180},
    Pages = {32-36},
    Title = {A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems},
    Year = {2002},
    }  
    

41. C. Bolchini, F. Salice and D. Sciuto, "Designing Self-Checking FPGAs through Error Detection Codes," in Proc. IEEE Defect and Fault Tolerance in VLSI Systems Symposium, pp. 60-68, November 2002 bibtex

    @inproceedings{DFT2002,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Defect and Fault Tolerance in VLSI Systems Symposium},
    Doi = {10.1109/DFTVS.2002.1173502},
    Keywords = {FPGA, Error Detecting Codes},
    Month = {November},
    Pages = {60-68},
    Title = {Designing Self-Checking {FPGA}s through Error Detection Codes},
    Url = {http://dx.doi.org/10.1109/DFTVS.2002.1173502},
    Year = {2002},
    }  
    

42. C. Bolchini and F. Salice, "A Software Methodology for Detecting Hardware Faults in VLIW Data Paths," in Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems, pp. 170-179, 2001 bibtex

    @inproceedings{DFT2001,
     Author = {Cristiana Bolchini and Fabio Salice},
    Booktitle = {Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2001.966766},
    Keywords = {VLIW, Fault Detection, Software Techniques},
    Pages = {170-179},
    Title = {A Software Methodology for Detecting Hardware Faults in VLIW Data Paths},
    Year = {2001},
    }  
    

43. C. Bolchini, L. Pomante, F. Salice and D. Sciuto, "On-line fault detection in a hardware/software co-design environment," in Proc. IEEE/ACM Intl Symp. on System Synthesis, pp. 51-56, 2001 bibtex

    @inproceedings{ISSS2001,
     Author = {Cristiana Bolchini and Luigi Pomante and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE/ACM Intl Symp. on System Synthesis},
    Doi = {http://doi.acm.org/10.1145/500001.500013},
    Keywords = {HW/SW CO-Design, On-Line Fault Detection},
    Pages = {51-56},
    Title = {On-line fault detection in a hardware/software co-design environment},
    Year = {2001},
    }  
    

44. C. Bolchini, L. Pomante, F. Salice and D. Sciuto, "Reliability Properties Assessment at System Level: A Co-design Framework," in Proc. IEEE Intl On-Line Testing Workshop, pp. 165-171, 2001 bibtex

    @inproceedings{IOLTW2001b,
     Author = {Cristiana Bolchini and Luigi Pomante and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Intl On-Line Testing Workshop},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937837},
    Pages = {165-171},
    Read = {No},
    Title = {Reliability Properties Assessment at System Level: A Co-design Framework},
    Year = {2001},
    }  
    

45. C. Bolchini, F. Salice and D. Sciuto, "Designing Reliable Embedded Systems Based on 32 Bit Microprocessors," in Proc. IEEE Intl On-Line Testing Workshop, pp. 137, 2001 bibtex

    @inproceedings{IOLTW2001a,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Intl On-Line Testing Workshop},
    Pages = {137},
    Title = {Designing Reliable Embedded Systems Based on 32 Bit Microprocessors},
    Year = {2001}
    }  
    

46. C. Bolchini, F. Salice and D. Sciuto, "A synthesis methodology aimed at improving the quality of TSC devices," in Proc. IEEE Intl Symp Defect and Fault Tolerance in VLSI Systems, pp. 247-255, 1999 bibtex

    @inproceedings{DFT1999,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Intl Symp Defect and Fault Tolerance in VLSI Systems},
    Doi = {http://dx.doi.org/10.1109/DFTVS.1999.802891},
    Keywords = {Self-Checking Circuits},
    Pages = {247-255},
    Title = {A synthesis methodology aimed at improving the quality of TSC devices},
    Year = {1999},
    }  
    

47. A. Allara, C. Bolchini, P. Cavalloro, S. Comai and D. Sciuto, "Guidelines for Property Verification of VHDL Models: an Industrial Perspective," in Proc. Forum on Design Languages, pp. 11-20, 1998 bibtex

    @inproceedings{FDL1998,
     Author = {Alberto Allara and Cristiana Bolchini and Patrizia Cavalloro and Sara Comai and Donatella Sciuto},
    Booktitle = {Proc. Forum on Design Languages},
    Pages = {11-20},
    Title = {Guidelines for Property Verification of VHDL Models: an Industrial Perspective},
    Year = {1998}
    }  
    

48. C. Bolchini, W. Fornaciari, F. Salice and D. Sciuto, "Concurrent Error Detection at Architectural Level," in Proc. IEEE/ACM Intl. Symp. on System Synthesis, pp. 72-75, 1998 bibtex

    @inproceedings{ISSS1998,
     Author = {Cristiana Bolchini and William Fornaciari and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE/ACM Intl. Symp. on System Synthesis},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/ISSS.1998.730600},
    Keywords = {Concurrent Error Detection, Architectural Level},
    Pages = {72-75},
    Title = {Concurrent Error Detection at Architectural Level},
    Year = {1998},
    }  
    

49. C. Bolchini, F. Salice and D. Sciuto, "Fault Analysis in Networks with Concurrent Error Detection Properties," in Proc. IEEE Conf. Design, Automation and Test in Europe, pp. 957-958, 1998 bibtex

    @inproceedings{DATE1998,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Conf. Design, Automation and Test in Europe},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DATE.1998.655987},
    Keywords = {Fault-Error Classification, Error Detecting Codes},
    Pages = {957-958},
    Title = {Fault Analysis in Networks with Concurrent Error Detection Properties},
    Year = {1998},
    }  
    

50. C. Bolchini, F. Salice and D. Sciuto, "A Novel Methodology for Designing TSC Combinational Networks based on the Parity Bit Code," in Proc. European Design and Test Conference, pp. 440--444, 1997 bibtex

    @inproceedings{EDTC1997,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. European Design and Test Conference},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/EDTC.1997.582397},
    Keywords = {Error Detecting Codes, Self-Checking Circuits},
    Pages = {440--444},
    Title = {A Novel Methodology for Designing TSC Combinational Networks based on the Parity Bit Code},
    Year = {1997},
    }  
    

51. C. Bolchini, G. Buonanno, D. Sciuto and R. Stefanelli, "An Improved Fault tolerant Architecture at CMOS Level," in Proc. Int. Symposium on Circuits And Systems, pp. 2737-2740, 1997 bibtex

    @inproceedings{ISCAS1997b,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. Int. Symposium on Circuits And Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.1997.612891},
    Keywords = {CMOS},
    Pages = {2737-2740},
    Title = {{An Improved Fault tolerant Architecture at CMOS Level}},
    Year = {1997},
    }  
    

52. C. Bolchini, F. Salice and D. Sciuto, "Conditions for the Design of Circuits with Concurrent Error Detection properties," in Proc. IEEE Int. Symposium on Circuits And Systems, pp. 2741-2744, 1997 bibtex

    @inproceedings{ISCAS1997a,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Int. Symposium on Circuits And Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.1997.612892},
    Keywords = {Concurrent Error Detection},
    Pages = {2741-2744},
    Title = {Conditions for the Design of Circuits with Concurrent Error Detection properties},
    Year = {1997},
    }  
    

53. C. Bolchini, F. Salice and D. Sciuto, "Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks," in Proc. IEEE 7th Great Lakes Symposium on VLSI, pp. 32-37, 1997 bibtex

    @inproceedings{GLSVLSI1997,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE 7th Great Lakes Symposium on VLSI},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/GLSV.1997.580407},
    Keywords = {Parity Code, TSC circuit, Fault Observability},
    Pages = {32-37},
    Title = {Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks},
    Year = {1997},
    }  
    

54. C. Bolchini, F. Salice and D. Sciuto, "A TSC Evaluation Function for Combinational Circuits," in Proc. IEEE Int. Conference on Computer Design, pp. 555-560, 1997 bibtex

    @inproceedings{ICCD1997,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Int. Conference on Computer Design},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628921},
    Keywords = {TSC cost function, Reliability},
    Pages = {555-560},
    Title = {A TSC Evaluation Function for Combinational Circuits},
    Year = {1997},
    }  
    

55. C. Bolchini, F. Salice and D. Sciuto, "Designing Networks with Error Detection Properties through the Fault-Error Relation," in Proc. IEEE Workshop on Defect and Fault-Tolerance in VLSI Systems, pp. 290-297, 1997 bibtex

    @inproceedings{DFT1997a,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Workshop on Defect and Fault-Tolerance in VLSI Systems},
    Doi = {http://dx.doi.org/10.1109/DFTVS.1997.628336},
    Keywords = {Fault-Error Relation, Fault Detection, Self-Checking Circuits},
    Pages = {290-297},
    Title = {Designing Networks with Error Detection Properties through the Fault-Error Relation},
    Year = {1997},
    }  
    

56. C. Bolchini, G. Buonanno, M. Cozzini, D. Sciuto and R. Stefanelli, "Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks," in Proc. IEEE Workshop on Defect and Fault-Tolerance in VLSI Systems, pp. 204-211, 1997 bibtex

    @inproceedings{DFT1997b,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Marco Cozzini and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. IEEE Workshop on Defect and Fault-Tolerance in VLSI Systems},
    Doi = {http://dx.doi.org/10.1109/DFTVS.1997.628326},
    Keywords = {CMOS, EDC, Fault Tolerance},
    Pages = {204-211},
    Title = {Designing Ad-Hoc Codes for the Realization of Fault Tolerant {CMOS} Networks},
    Year = {1997},
    }  
    

57. C. Bolchini, G. Buonanno, D. Sciuto and R. Stefanelli, "Static Redundancy Techniques for CMOS Gates," in Proc. Int. Symposium on Circuits And Systems, pp. 576-579, 1996 bibtex

    @inproceedings{ISCAS1996,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. Int. Symposium on Circuits And Systems},
    Pages = {576-579},
    Title = {Static Redundancy Techniques for CMOS Gates},
    Year = {1996}
    }  
    

58. C. Bolchini, F. Salice and D. Sciuto, "Redundant Faults in TSC Networks: Definition and Removal," in Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems, pp. 277-285, 1996 bibtex

    @inproceedings{DFT1996a,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.1996.572034},
    Keywords = {TSC circuit, Redundant Faults},
    Pages = {277-285},
    Title = {{Redundant Faults in TSC Networks: Definition and Removal}},
    Year = {1996},
    }  
    

59. C. Bolchini, G. Buonanno, D. Sciuto and R. Stefanelli, "Fault detection and fault tolerance issues at CMOS level through AUED encoding," in Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems, pp. 258-266, 1996 bibtex

    @inproceedings{DFT1996b,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.1996.572032},
    Keywords = {CMOS, Error Detecting Codes},
    Pages = {258-266},
    Title = {{Fault detection and fault tolerance issues at CMOS level through AUED encoding}},
    Year = {1996},
    }  
    

60. C. Bolchini, L. Baresi and D. Sciuto, "Software methodologies for VHDL Code Static Analysis based on Flow Graphs," in Proc. EuroDAC with EuroVHDL, pp. 406-411, 1996 bibtex

    @inproceedings{EUROVHDL1996,
     Annote = {Best Paper Nominee},
    Author = {Cristiana Bolchini and Luciano Baresi and Donatella Sciuto},
    Booktitle = {Proc. EuroDAC with EuroVHDL},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/EURDAC.1996.558236},
    Keywords = {VHDL},
    Pages = {406-411},
    Title = {Software methodologies for VHDL Code Static Analysis based on Flow Graphs},
    Year = {1996},
    }  
    

61. C. Bolchini, F. Salice and D. Sciuto, "Design of Totally Self Checking Checkers for a class of Hamming Distance Codes," in Proc. IEEE 2nd Int. On Line Testing Workshop, pp. 150-153, 1996 bibtex

    @inproceedings{IOLTW1996,
     Author = {Cristiana Bolchini and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE 2nd Int. On Line Testing Workshop},
    Keywords = {Error Detecting Codes},
    Pages = {150-153},
    Title = {Design of Totally Self Checking Checkers for a class of Hamming Distance Codes},
    Year = {1996}
    }  
    

62. C. Bolchini, R. Montandon, F. Salice and D. Sciuto, "A State Encoding for Self-Checking Finite State Machines," in Proc. IEEE ASP-DAC and VLSI'95, pp. 711-716, 1995 bibtex

    @inproceedings{ASPDAC1995,
     Author = {Cristiana Bolchini and Roberto Montandon and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE ASP-DAC and VLSI'95},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1995.486392},
    Keywords = {State Encoding, Fault Detection, Self-Checking Circuits},
    Pages = {711-716},
    Title = {A State Encoding for Self-Checking Finite State Machines},
    Year = {1995},
    }  
    

63. C. Bolchini, R. Montandon, F. Salice and D. Sciuto, "Self-checking FSMs based on a constant distance state encoding," in Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems, pp. 271-277, 1995 bibtex

    @inproceedings{DFT1995,
     Author = {Cristiana Bolchini and Roberto Montandon and Fabio Salice and Donatella Sciuto},
    Booktitle = {Proc. IEEE Int. Symposium Defect and Fault Tolerance in VLSI Systems},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.1995.476961},
    Keywords = {Error Detecting Codes},
    Pages = {271-277},
    Title = {Self-checking {FSMs} based on a constant distance state encoding},
    Year = {1995},
    }  
    

64. C. Bolchini, G. Buonanno, D. Sciuto and R. Stefanelli, "Innovative Design of CMOS Fault Tolerant Structures," in Proc. Wafer Scale Integration, pp. 267-276, 1995 bibtex

    @inproceedings{WSI1995b,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. Wafer Scale Integration},
    Doi = {http://dx.doi.org/10.1109/ICWSI.1995.515461},
    Keywords = {CMOS, Fault Tolerance},
    Pages = {267-276},
    Title = {Innovative Design of {CMOS} Fault Tolerant Structures},
    Year = {1995},
    }  
    

65. C. Bolchini, M. Bombana, P. Cavalloro, P. Cavalloro, F. Ferrandi, D. Sciuto and G. Zaza, "Towards WSI Testable Devices: an Improved Scan Insertion Technique," in Proc. Wafer Scale Integration, pp. 339-348, 1995 bibtex

    @inproceedings{WSI1995a,
     Author = {Cristiana Bolchini and Massimo Bombana and Patrizia Cavalloro and Patrizia Cavalloro and Fabrizio Ferrandi and Donatella Sciuto and Giuseppe Zaza},
    Booktitle = {Proc. Wafer Scale Integration},
    Doi = {http://dx.doi.org/10.1109/ICWSI.1995.515468},
    Keywords = {Scan},
    Pages = {339-348},
    Title = {Towards WSI Testable Devices: an Improved Scan Insertion Technique},
    Year = {1995},
    }  
    

66. C. Bolchini, F. Fummi, R. Gemelli and F. Salice, "A BDD Based Algorithm for Detecting Difficult Faults," in Proc. Int. Symposium on Circuits And Systems, pp. 2015-2018, 1995 bibtex

    @inproceedings{ISCAS1995b,
     Author = {Cristiana Bolchini and Franco Fummi and Roberto Gemelli and Fabio Salice},
    Booktitle = {Proc. Int. Symposium on Circuits And Systems},
    Doi = {http://dx.doi.org/10.1109/ISCAS.1995.523818},
    Pages = {2015-2018},
    Title = {A {BDD} Based Algorithm for Detecting Difficult Faults},
    Year = {1995},
    }  
    

67. C. Bolchini and D. Sciuto, "An Output|State Encoding for Self-Checking Finite State Machines," in Proc. Int. Symposium on Circuits And Systems, vol. 3, pp. 2136-2139, 1995 bibtex

    @inproceedings{ISCAS1995a,
     Author = {Cristiana Bolchini and Donatella Sciuto},
    Booktitle = {Proc. Int. Symposium on Circuits And Systems},
    Doi = {http://dx.doi.org/10.1109/ISCAS.1995.523848},
    Keywords = {Error Detecting Codes},
    Pages = {2136-2139},
    Title = {An Output|State Encoding for Self-Checking Finite State Machines},
    Volume = {3},
    Year = {1995},
    }  
    

68. C. Bolchini, M. Bombana, G. Buonanno, P. Cavalloro, F. Ferrandi and D. Sciuto, "Assessment of functional testability properties from VHDL descriptions," in Proc. VHDL-Forum Europe, pp. 84-95, 1995 bibtex

    @inproceedings{VHDLFORUM1995,
     Author = {Cristiana Bolchini and Massimo Bombana and Giacomo Buonanno and Patrizia Cavalloro and Fabrizio Ferrandi and Donatella Sciuto},
    Booktitle = {Proc. VHDL-Forum Europe},
    Doi = {VHDL},
    Pages = {84-95},
    Title = {Assessment of functional testability properties from VHDL descriptions},
    Year = {1995},
    }  
    

69. C. Bolchini, G. Buonanno, D. Sciuto and R. Stefanelli, "A New Switching Level Approach To Multiple Output Functions Synthesis," in Proc. 8th Int. Conf. on VLSI Design, pp. 125-129, 1995 bibtex

    @inproceedings{VLSI1995,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. 8th Int. Conf. on VLSI Design},
    Doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512090},
    Keywords = {CMOS},
    Pages = {125-129},
    Title = {A New Switching Level Approach To Multiple Output Functions Synthesis},
    Year = {1995},
    }  
    

70. C. Bolchini, "CASTOR: A Computer Aided System Testability OptimizeR," in Proc. EUROMICRO'94 System Architecture and Integration, pp. 314-321, 1994 bibtex

    @inproceedings{EUROMICRO94,
     Author = {Cristiana Bolchini},
    Booktitle = {Proc. EUROMICRO'94 System Architecture and Integration},
    Doi = {http://dx.doi.org/10.1109/EURMIC.1994.390378},
    Keywords = {CASTOR, Design for Testability},
    Pages = {314-321},
    Title = {{CASTOR: A Computer Aided System Testability OptimizeR}},
    Year = {1994},
    }  
    

71. G. Bezzi, C. Bolchini, I. Bolzoni, M. Bombana, G. Buonanno, S. Cant\`u, P. Cavalloro, F. Fummi, D. Sciuto and G. Zaza, "CASTOR: An Expert Advisor for Testability Enhancements of VLSI Systems," in Proc. IEEE CAIA, pp. 9-15, 1994 bibtex

    @inproceedings{CAIA94,
     Author = {Giovanni Bezzi and Cristiana Bolchini and Ivan Bolzoni and Massimo Bombana and Giacomo Buonanno and Stefano Cant\`u and Patrizia Cavalloro and Franco Fummi and Donatella Sciuto and Giuseppe Zaza},
    Booktitle = {Proc. IEEE CAIA},
    Doi = {http://dx.doi.org/10.1109/CAIA.1994.323698},
    Keywords = {CASTOR, Design for Testability},
    Pages = {9-15},
    Title = {CASTOR: An Expert Advisor for Testability Enhancements of VLSI Systems},
    Year = {1994},
    }  
    

72. G. Bezzi, C. Bolchini, I. Bolzoni, S. Cant\`u, F. Fummi and D. Sciuto, "Design for Testability Issues in the Implementation of Sequential Array Architectures," in Proc. IEEE Int. Conference on Wafer Scale Integration, pp. 169-178, 1994 bibtex

    @inproceedings{WSI94,
     Author = {Giovanni Bezzi and Cristiana Bolchini and Ivan Bolzoni and Stefano Cant\`u and Franco Fummi and Donatella Sciuto},
    Booktitle = {Proc. IEEE Int. Conference on Wafer Scale Integration},
    Doi = {http://dx.doi.org/10.1109/ICWSI.1994.291254},
    Keywords = {Design for Testability},
    Pages = {169-178},
    Title = {Design for Testability Issues in the Implementation of Sequential Array Architectures},
    Year = {1994},
    }  
    

73. C. Bolchini, G. Buonanno, D. Sciuto and R. Stefanelli, "A CMOS Fault Tolerant Architecture for Swith-Level Faults," in Proc. IEEE Workshop on Defect and Fault-Tolerance in VLSI Systems, DFT, pp. 10-18, October 1994 bibtex

    @inproceedings{DFT1994,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. IEEE Workshop on Defect and Fault-Tolerance in VLSI Systems, DFT},
    Doi = {http://dx.doi.org/},
    Isbn = {0-8186-6307-3},
    Keywords = {CMOS, Fault Tolerance},
    Location = {Montr{\'e}al, Canada},
    Month = {October},
    Pages = {10-18},
    Title = {A {CMOS} Fault Tolerant Architecture for Swith-Level Faults},
    Year = {1994},
    }  
    

74. C. Bolchini, G. Buonanno, D. Sciuto and R. Stefanelli, "CMOS Reliability Improvements Through a New Fault Tolerant Technique," in Proc. IEEE Int. Symposium on Circuits and Systems, ISCAS, vol. 4, pp. 83-86, 1994 bibtex

    @inproceedings{ISCAS1994a,
     Author = {Cristiana Bolchini and Giacomo Buonanno and Donatella Sciuto and Renato Stefanelli},
    Booktitle = {Proc. IEEE Int. Symposium on Circuits and Systems, ISCAS},
    Doi = {http://dx.doi.org/10.1109/ISCAS.1994.409202},
    Keywords = {CMOS, Fault Tolerance},
    Pages = {83-86},
    Title = {{CMOS} Reliability Improvements Through a New Fault Tolerant Technique},
    Volume = {4},
    Year = {1994},
    }  
    

75. C. Bolchini, F. Fummi and D. Sciuto, "Two-Dimensional Sequential Array Architectures: Design for Testability Approaches," in Proc. IEEE Int. Symposium on Circuits and Systems, ISCAS, vol. 4, pp. 81-84, 1994 bibtex

    @inproceedings{ISCAS1994b,
     Author = {Cristiana Bolchini and Franco Fummi and Donatella Sciuto},
    Booktitle = {Proc. IEEE Int. Symposium on Circuits and Systems, ISCAS},
    Doi = {http://dx.doi.org/10.1109/ISCAS.1994.408760},
    Keywords = {Two-dimensional arrays, Design for Testability},
    Pages = {81-84},
    Title = {Two-Dimensional Sequential Array Architectures: Design for Testability Approaches},
    Volume = {4},
    Year = {1994},
    }
    

76. C. Bolchini, M. Bombana, P. Cavalloro, C. Costi, F. Fummi and G. Zaza, "A design methodology for the correct specification of VLSI systems," in Proc. EUROMICRO'93 Hardware and Software Design Automation, Microprocessing and Microprogramming, vol. 38, pp. 563-570, 1993 bibtex

    @inproceedings{EUROMICRO93b,
     Author = {Cristiana Bolchini and M. Bombana and P. Cavalloro and C. Costi and F. Fummi and G. Zaza},
    Booktitle = {Proc. EUROMICRO'93 Hardware and Software Design Automation, Microprocessing and Microprogramming},
    Doi = {http://dx.doi.org/10.1016/0165-6074(93)90196-R},
    Pages = {563-570},
    Title = {A design methodology for the correct specification of VLSI systems},
    Volume = {38},
    Year = {1993},
    }  
    

77. C. Bolchini and F. Fummi, "FSM Fault Models Impact on Test Performances," in Proc. EUROMICRO'93 Hardware and Software Design Automation, Microprocessing and Microprogramming, vol. 38, pp. 229-236, 1993 bibtex

    @inproceedings{EUROMICRO93a,
     Author = {Cristiana Bolchini and Franco Fummi},
    Booktitle = {Proc. EUROMICRO'93 Hardware and Software Design Automation, Microprocessing and Microprogramming},
    Doi = {http://dx.doi.org/10.1016/0165-6074(93)90149-F},
    Pages = {229-236},
    Title = {FSM Fault Models Impact on Test Performances},
    Volume = {38},
    Year = {1993},
    }