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Up to now, Alfio Zanchi has been involved in theoretical, simulation and experimental activity in the field of RF circuits for wireless front-end. This  research work is documented in some peer-reviewed scientific publications; some interesting topics are outlined here in the following.

The former section of the Ph.D. work led to devise a simple relationship between the Single Sideband to Carrier Ratio (SSCR) taken at offset f_n away from the carrier at f₀, and the cycle-to-cycle time jitter (s_To) of the period of an oscillator. The relationship found holds for the classical 1/f_n² shape of the phase noise:

This link was experimentally verified by means of a CMOS ring oscillator, by adopting a spectrum analyzer to assess the SSCR (frequency domain), and a Time-to-Amplitude Converter (TAC) in order to measure the jitter of the period (time domain) [J1].

Output spectrum of a ring CMOS oscillator : SSCR(40 kHz) = -98 dBc/Hz	Time jitter of the oscillation period (1 ch. = 5.44 ps).  The intrinsic uncertainty of the measurement system  amounts to 3.4 ps rms

The frequency-time domain link has been extended then to a general phase noise shape, by resorting to a slightly more complex relation that can be efficiently exploited in numerical way:

This general formula has been successfully validated through the simulation (with Matlab®) of the popular case of PLL-based frequency synthesizers. The phase noise spectrum near the carrier is filtered by the loop action, and the time jitter of the period diminishes accordingly (14% with a PLL bandwidth as high as f₀/10) [S4] .

The details of spectra of the simulated signals close to the carrier frequency (1 GHz).  The upper spectrum refers to the case of oscillators affected by  white frequency noise (free-running VCO),  the lower one to a highpass-filtered frequency noise (PLL synthesizer)

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Sensitivity analysis for the SSCR

From a more practical standpoint, the dominant part of the work concerned the effects that cause a phase noise degradation in LC-Tuned VCO’s, when they are forced to operate at high oscillation amplitudes. In effect, despite the general formula for the accounting of the SSCR reads [J2] :

thus indicating an improvement when the carrier power is raised, from the measurements performed on some RF demonstrators for DAB applications (Digital Audio Broadcasting) the SSCR was observed to reach a minimum and then steeply rise as the oscillation amplitude increased. This behavior sets a limit to the range where better performance can be traded against higher power dissipation.

On a differential LC-tuned VCO fabricated in high-speed bipolar technology, whose schematic is depicted here aside, we tried to carry on further attempts to quantitatively explain the SSCR behavior against the amplitude.  At a first glance, the most likely source of amplitude-dependent phase noise instability was the AM-to-PM conversion [P1]. A preliminary theoretical study on the static characteristic of the tank was made, that proved to be consistent with the results of simulations both at behavioral level (Matlab modeling and analysis of the non-linearity of the tank) and at circuit level (Eldo software supported by STMicroelectronics models) [S3]. The conversion effect can explain the rise in SSCR at least from a qualitative point of view; but, once an experimental countercheck was performed through the injection of known amounts of noise in the circuit, it was found to be too small an effect as for quantitative predictions [P2] .

Schematic structure of the tested VCO. The LC tank is fully integrated on the silicon chip

Here below is depicted the AM-to-PM conversion coefficient (that we called K_Vo) as it was derived after a sensitivity-fashion equation such as:

Also, a device-level analysis has been carried out on the varactors of the tank, to clarify whether they could give rise to Q-loading effects [P1]. During the instants in which the varactor diodes are almost forward-biased, due to the positive peak of the oscillating voltage on the tank, direct currents can flow in fact into them, and load the quality factor of the resonator.

KVo : AM-to-PM conversion factor on the tank as simulated by using the charge-control  varactor model of Anacad Eldo	Half-map of the dopant concentration regions issued in the vertical varactor structure, with the  metallurgical boron-phosphorus junction and the lateral anode sinker

The in-depth simulations performed with TCAD Dessis® onto the device structure reported in the figure above, indicated however that the slight worsening in the AM-to-PM conversion efficiency could not account for the phase noise degradation actually noticed at high values of A₀. The SSCR vs. amplitude dependence was instead fully explained by taking into account the low-frequency noise coupling to the tail of the differential VCO topology under test.

Not only noise and disturbances are transferred to the tank, but they also modulate the phase delay of the VCO loop due to the presence of active elements. Experimental and simulation procedures for the evaluation of this effect and of their impact on the circuit performance were considered, and are summarized in the next figure [J2] .

The solid curves show the SSCR vs. A0 as measured on the VCO, with the lower rail VEE connected to a band-gap voltage reference with SnV = 120 nV/éHz (solid curve with triangles) and directly to a cleaner ground (solid curve with circles).  The base-line A was derived from the traditional non-linear theory that takes into account the switching regime of the circuit, and keeps decreasing.  Curves B and C have been evaluated considering also the modulation of the phase delay of the transconductor due to the low-frequency noise.

Why does the circuit seem sensitive to the low frequency noise coming from the tail? The answer is found in the two pictures reported beneath :

Dependence of the oscillation frequency on IT (solid line, referred to the left axis).  The triangles (referred to the right axis) show  the coefficient KIT as evaluated from the derivative  dw0/dIT of the frequency curve.  The squares are the values obtained by injecting  harmonic current tones into the tail and computing the magnitude of the phase transfer: the results of the two methods match each other

Schematic representation of the LC-tuned oscillator, highlighting the load due to the transconductor and  its internal delay. The transconductor input impedance, in parallel  to the tank, is essentially due to the base spreading resistance rbb' and to the diffusion capacitance Cp.  In fact, at w0 the base resistance rp is much larger  than the impedance of Cp.. In effect, both the  input impedance of the transconductor and the  transistor transit time depend on IT and add a phase delay  Dqloop to the feedback loop. According to the Barkhausen  criterion, the oscillation frequency is therefore  shifted away from the resonance frequency of the tank.

The oscillation frequency is a function of the phase delay met within the loop, Dq_loop, and is obviously expected to depend on I_T since it is [P2] :

This is exactly what we observe in the first graph. Taking the current noise S_IT = 2.4 nA/éHzdue to the band-gap, and converting it into phase noise via the K_IT sensitivity coefficient, the dashed line (B) previously highlighted is recovered, that perfectly matches the experimental values.
When taking the phase delay Dq_loop obtained changing the tail current I_T in the simulation of the open-loop circuit for computing the actual w₀, we obtain again the frequency vs. amplitude dependence already observed from the circuit-level simulations.

In summary, the results confirm that the SSCR performance of the VCO is limited by the frequency sensitivity to the low frequency noise affecting the biasing current.
 
 
 

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As a byproduct of the simulation activity, some experimental and simulation techniques were devised that can be adopted to assess the importance of the sensitivity effect in other oscillator topologies too [P3]. The sensitivity analysis, based on the evaluation of derivatives like dw₀/dI_T, was proven equivalent to the traditional time-domain analysis performed by injecting low frequency harmonic tones into the circuit. The same approach can be also adopted in simulation, in place of the more time-consuming tone injection techniques, allowing for fast and accurate predictions of phase noise in oscillators even adopting inexpensive software, such as PSpice®.
Then a first, much faster technique based on sensitivity analysis was proposed, suitable for the estimation of phase noise due to low-frequency sources, e.g. 1/f noise. Finally, the high-frequency noise sources contribution to SSCR was analyzed through another alternative method based on the frequency demodulation of the carrier. Both of these methods allow the designer to quickly identify the noise sources mainly responsible for the instability of the carrier.

Comparison of three simulation techniques for the estimation of phase noise in oscillators.  The CPU time required by each method accounts  for both the Eldo simulation and the post-processing time  (FFT for the traditional, differentiation for the sensitivity,  and frequency extraction for the demodulation method)

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A separate branch of the research activity involved the study of the effects on the phase noise of a VCO, due to the presence of an eventual AAC [S1] .
The Automatic Amplitude Control (AAC) system is an increasingly popular servo-circuit for integrated VCOs, that provides control on the A₀ in steady state and on the start-up transient. Nevertheless, the noise contributed to the oscillator by the AAC can degrade the phase noise performance of the overall synthesizer. In particular, the time-varying noise transfer function of the switching peak detector needed in the feedback path was analyzed, recognizing it as the critical noise source in the loop.
The circuit senses the amplitude of the oscillation and can regulate it at the phase noise optimum, by reacting onto the VCO cell bias current.

 

Block diagram of the control system.  The output noise of the peak detector is not compensated for  by the loop, as it comes embedded in the feedback path

The Matlab-Simulink® simulations of the time-varying noise gave rise to a collection of 2-D autocorrelation R_yy(t₀ , t₁), one for each trial of the stochastic process, that had to be further processed in order to gain statistical significance and obtain back a 1-D ergodic function.
 
 

+++... _________________________________________________________________________________________________ N

Ensemble average of N single-realization autocorrelations. The surfaces are obtained in the case of a peak detector with 50% duty cycle

A 2-D time average, which can be performed in lieu of the required ensemble average thanks to the low-pass filtering action of the dominant pole, finally gives the autocorrelation surface :

Autocorrelation averaged over 1000 statistically independent simulation trials,  for a peak detector featuring 50% duty cycle

Fortunately enough, such a R_yy(t₀ , t₁) can be filtered so as to translate it into a numerically manageable 1-D autocorrelation, suitable for Fourier transformation.  The main result of this study concerned the identification of a rule that holds for the noise at the output of the stage: whether it comes from the resistor of the peak detector or from the rectifier diode, the current noise entering the block undergoes a filtering with constant GBWP. Although the noise filtering is quite complex owing to time-variance, this property is transmitted to the spectrum profile at the output of this stage, as clearly shown by the next figure.

Simulated noise power density spectra for increasing  duty cycles of the peak detector switching regime. The 0% d.c. level has been set to –54 dBV2/Hz

Further experimental validation of this characteristic was carried out by means of a discrete-components test board.

By exploiting this regularity of the output’s behavior, the seemingly severe problem of predicting the output spectrum can be successfully faced and overcome. From the analysis of the filter mechanisms, fast rules to predict the noise spectral density at the peak detector output can be sought. The final rules that can be used to account for the peak detector output noise are:

where t_ON and t_OFF are determined by the d.c. of the block, and it was defined a = exp(-T_OFF/T)  and b = exp(-T_ON/T) [S1].

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The theoretical and simulation work finally culminated in the design of some test structures of VCO. One of the most interesting topologies that were paid attention is the differential Colpitts. It consisted of two Colpitts-Clapp oscillators coupled back-to-back with two common-mode quenching resistors, purposely placed on the symmetry axis of the oscillator.
As for all of the other VCO circuits, the Colpitts stage was accurately sized and simulated, and the layout was finally produced. An example of the final design that has been diffused on silicon is reported in the figure here below:

Cadence layout of the  mirrored-Colpitts oscillator. The symmetry principle lies behind the common-mode damping,  and is exploited in the synchronization  of the two halves of the VCO

Up to 3 circuits of this kind have been accommodated into a single test chip with TQFP48 package. The final product of the project pursued during the Ph.D. were 6 test chips, arranged as depicted in the first figure below, that allowed separate characterization of the phase noise performance of each VCO. Also shown is a microphotograph of one of the VCOs finally diffused on silicon
 
 

The test chip CHIP-II as arranged for the eventual  silicon run. The common substrate has been split apart  in order to cancel out any noise source that may couple to the VCO under operation. The RF oscillation output paths have been kept the shortest, both from routing and bonding standpoints

Here is a microphotograph of the VCO with  the AAC system beneath it. The 2-turn spiral inductor  can be viewed on top of the circuit, along with the  central column of 12 varactors and 2 fixed-value,  metal-to-metal capacitors.  The  block with small vertical pitch placed under the tank  is the VCO transconductor, holding 6 maximum-size  bipolar transistors. The large capacitors seen to  the bottom left of the image make up the dominant pole  of the AAC, while the capacitor of the passive peak detector  lies to the bottom right.

The last step towards the test of the circuits designed is the RF board preparation. The test cards have been realized with 4-layers, in standard FR4 dielectric material, with properly tailored gold-over-copper traces. The large epoxy component screwed over the card is a high-performance RF socket (Johnstech® - Giga3 family) into which the previously chips are inserted and locked.

The RF board with mounted socket, bias voltage soldernails,  and standard SMA output plugs

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Since it was observed before how the phase noise performance of the local oscillators used in the RF front-ends is strictly related to the oscillation amplitude, in some test circuits the VCO tank-transconductor core was accompanied with an Automatic Amplitude Control loop (AAC). In the test, the SSCR obtained at the optimal oscillation amplitude condition was measured to reach down to –104.5 dBc/Hz at 100 kHz from the 2.56 GHz carrier. The measurements also show that the AAC assures a wide-range (from 50 mV up to 1.3 V) and fast-settling (<100 ns) amplitude regulation, even with 2.4 V supply [S2].

As compared to a standalone oscillator with the same core, thanks to the loop gain of the AAC regulator the controlled-amplitude VCO features up to 10-dB rejection of the spurious tones, noise and outer interference possibly inserting into the bias nodes of the circuit.

In conclusion, the performance of the structures designed:  as low as –104.5 dBc/Hz @ 100 kHz from the 2.56 GHz carrier.  The output spectrum sketched in the figure was measured in the  Circuits and Systems Lab  of the Electronics Dept. at the Politecnico di Milano

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He is now on the way to Texas Instruments, Data Converter design Group, where he will give his contribution in a mix of digital and analog design problems.

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