1.1.Original Contributions and Results.............................................. 5
1.1.1. Power Estimation............................................................... 6
1.1.2. Power Optimization............................................................ 8
1.2.Description by Chapters.......................................................... 10
2.1. Introduction......................................................................... 15
2.2. Design Abstraction Levels....................................................... 17
2.2.1. System-Level................................................................... 19
2.2.2. Algorithmic- or Behavioral-Level......................................... 23
2.2.3. Architectural- or RT-Level.................................................. 24
2.2.4. The Probabilistic Model for FSMs......................................... 25
2.3. Sources of Power Consumption................................................ 34
2.1.1. Power Optimization by Frequency Reduction......................... 40
2.1.2. Power Optimization by Voltage Scaling................................ 41
2.1.3. Power Optimization by Capacitance Reduction...................... 45
2.3.4. Power Optimization by Switching Activity Reduction............... 46
2.4. Power Optimization and Synthesis Techniques........................... 48
2.4.1. Software-Level Optimization.............................................. 48
2.4.2. Behavioral-Level Optimization............................................ 50
2.4.3. Behavioral-Level Synthesis................................................ 52
2.4.4. Architectural-Level Optimization......................................... 54
2.4.5. Logic-Level Optimization for Sequential Circuits.................... 57
2.4.6. Logic-Level Optimization for Combinational Circuits............... 59
2.4.7. Alternative Approaches...................................................... 62
2.5. Power
Estimation Techniques.................................................. 63
2.5.1. Software-Level Estimation................................................. 64
2.5.2. High-Level Estimation....................................................... 64
2.5.3. Logic-Level Estimation...................................................... 64
2.6. Summary.............................................................................. 67
3.1. Introduction......................................................................... 69
3.2. Previous Work on Software-Level Power Estimation.................... 74
3.3. The Target System Architecture............................................... 78
3.4. The Overall Software Evaluation Methodology............................ 80
3.4.1. The OCCAM2 Language...................................................... 82
3.4.2. The VIS Language............................................................ 84
3.4.3. The OCCAM2 to VIS Compilation......................................... 87
3.4.4. The VIS to Target Assembler Mapping................................. 91
3.4.5. The Software Back-Annotation............................................ 91
3.4.6. The Software Power Estimation.......................................... 92
3.4.7. The Software Power Profiling.............................................. 94
3.5. Summary.............................................................................. 95
4.1. Introduction......................................................................... 97
4.2. Previous Work on High-Level Power Estimation........................ 100
4.2.1. Behavioral-Level Power Estimation.................................... 101
4.2.2. Architectural-Level Power Estimation................................. 102
4.2.3. Pattern-Dependency........................................................ 105
4.3. The High-Level Power Estimation Model for the HW Part............ 106
4.4. PIO Estimation..................................................................... 107
4.5. PDP Estimation..................................................................... 108
4.5.1. PREG Estimation............................................................... 108
4.5.2. PMUX Estimation.............................................................. 112
4.5.3. PFU Estimation................................................................ 115
4.6. PMEM Estimation................................................................... 115
4.7. PCNTR Estimation.................................................................. 116
4.7.1. Switching Activity Estimation for the State Bit Lines............ 117
4.7.2. Switching Activity Estimation for the Primary Outputs.......... 118
4.7.3. PIN Estimation................................................................ 119
4.7.4. PSTATE_REG Estimation........................................................ 120
4.7.5. PCOMB
Estimation............................................................. 120
4.7.6. POUT Estimation.............................................................. 122
4.8. Implementation and Experimental Results............................... 122
4.9. Summary............................................................................ 132
5.1. Introduction........................................................................ 133
5.2. Previous Work on Bus Encoding Techniques............................. 137
5.3. Asymptotic Zero-Transition Encoding...................................... 143
5.3.1. Analytical Performance Comparison................................... 144
5.3.2. Experimental Performance Comparison............................... 144
5.4. Mixed Bus Encoding Techniques............................................. 148
5.4.1. T0_BI Encoding.............................................................. 148
5.4.2. Dual_T0 Encoding........................................................... 149
5.4.3. Dual_T0_BI Encoding...................................................... 150
5.4.4. Experimental Performance Comparison............................... 150
5.5. Encoding and Decoding Logic................................................. 152
5.5.1. Architectures.................................................................. 152
5.5.2. Power Analysis: On-Chip Buses......................................... 155
5.5.3. Power Analysis: Off-Chip Buses........................................ 155
5.6. Summary............................................................................ 157
6.1. Introduction........................................................................ 159
6.2. Previous Work on Power-Oriented Cache Modeling.................... 162
6.3. The System-Level Power Model.............................................. 166
6.3.1. The Memory Hierarchy Model............................................ 166
6.3.2. The Bus Encoder Model.................................................... 167
6.3.3. The Address and Data Stream Generator............................ 167
6.4. Simulation Methodology and Experimental Results.................... 172
6.4.1. Analysis of the Embedded System..................................... 174
6.4.2 Analysis of the High-End System....................................... 182
6.5. Summary............................................................................ 186
7.1. Introduction........................................................................ 189
7.2. Previous Work on State Encoding Techniques........................... 191
7.3. The Framework for Low-Power State Assignment...................... 194
7.3.1. State Ordering................................................................ 194
7.3.2. State Encoding............................................................... 197
7.4. Proposed Power-Oriented State Assignment Techniques............ 197
7.5. Experimental Results........................................................... 200
7.6. Summary............................................................................ 202
8.1. Thesis Summary by Chapters................................................. 204
8.2. Future Research.................................................................. 208