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| | CRISTINA
SILVANO
Link to CV
Link to Research
Statement
Short CV
She is an Associate Professor (with tenure) in Computer Engineering at Politecnico di
Milano, Department of Electronics and Computer Engineering, System
Architectures Group. Her
current primary research interests are in the area of
Computer Architectures and Electronic Design Automation, with particular emphasis on
design space exploration techniques and low-power design techniques for
multi-processor systems-on-chip. She is co-author of more than ninety
scientific publications
on peer-reviewed international journals and conferences (including 11 IEEE/ACM
Transactions and collecting one Best Paper Award). She
is co-author of the book: "Power Estimation and Optimization Methodologies for
VLIW-Based Embedded Systems", published
by Kluwer Academic Publisher (2003). She is co-editor of the books:
"Low-Power Networks-on-Chip", Springer (October 2010),
"Multi-objective design space exploration of
multiprocessor SoC architectures: the MULTICUBE approach" to be published by
Springer (2011) and
"Run-time Management techniques for Many-core Architectures" to be published
by Springer (2013). She holds three international
patents and she was co-inventor in
other eight international patents. She is Senior Member of IEEE and
Member of HiPEAC Network of
Excellence.
Education
She
received her Laurea Degree (M. Sc.) in Electronic Engineering
from Politecnico di Milano (Italy) in 1987 and her Ph. D. Degree in
Computer Engineering from University of
Brescia (Italy) on
March 1999 (XI) - Ph.D. Thesis title: “Power
Estimation and Optimization Methodologies for Digital Circuits and
Systems”.
Career
 | From
September 2002 to present, she is an Associate Professor (with tenure) in
Computer
Engineering at Politecnico di Milano, V
School of Engineering, Dipartimento di Elettronica e Informazione. Her
current primary research interests are in the area of
Computer Architectures and Electronic Design Automation, with particular emphasis on
design space exploration techniques and low-power design techniques for
multi-processor systems-on-chip. From
2005, she is also
collaborating with ALaRI-Advanced Learning and Research
Institute, part of the Faculty of Informatics of the University of Lugano (CH).
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| From
October 2000 to September 2002, she was Assistant Professor in Computer Science at
University of Milan, School of
Mathematical Physical and Natural Sciences, Department
of Computer Science.
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| From
September 1999 to September 2000, she was Post-Doctoral Researcher at the Dipartimento di Elettronica e
Informazione, Politecnico di Milano. Her research
activities were mainly related to the research contract: “Power
estimation methodologies for VLIW
architectures”, in collaboration with the Advanced
System Technology Division of ST Microelectronics. The
research activity carried out aimed at defining a power estimation and
optimization methodology for VLIW (Very Long Instruction Word) architectures
based on the Lx/ST200
family of VLIW embedded processor cores (developed as a partnership
between HP Labs and STMicroelectronics). The ST200 family (including the
ST210, ST220, ST231 processor cores) is used today for embedded media
processing in a variety of audio, video and imaging consumer
products.
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| From
November 1998 to August 1999, she was a Consultant Researcher in the
Electronic Design Automation Area at CEFRIEL (Center for the Research and
the Education in Information Engineering) in Milan. The research activity
carried out aims at defining a more general HW/SW co-design environment for
control dominated embedded systems. This work is part of the co-design
project named TOSCA (Tools for System Co-design Automation) and the European
Project No. 26796 PEOPLE (Power Estimation for fast exPLoration of Embedded
systems).
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| From
March 1996 to October 1998, she was with the Dipartimento di Elettronica per
l’Automazione, Università degli Studi di Brescia (Italy), where she was
pursuing her Ph. D. Degree in
Computer Engineering. She
received the Ph. D. Degree on
March 1999 discussing her thesis titled: “Power
Estimation and Optimization Methodologies for Digital Circuits and
Systems”. (Advisor:
Prof. P. Gubian, Università degli
Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano).
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| From
May 1987 to February 1996, she was with Groupe
Bull (also known as Bull HN Information Systems), where
she held the position of Senior
Design Engineer in the ASIC Development and Validation Group,
Research & Development Labs in Pregnana M. (Italy). She participated in the
design of several VLSI circuits for Bull computer systems. She has also been
involved in the definition of design and
simulation methodologies at the system-level. From 1992, she was part of the
Bull - IBM (Austin-USA) team for the design of the first multiprocessor
systems based on PowerPC processor architecture. These systems have been
fully designed in the Bull R&D Labs in Italy and then commercialized as
Bull Escala Servers and IBM RS/6000 Symmetric Multiprocessor
Servers. These
shared-memory multiprocessor systems are symmetric and scalable up to
eight processors. The architecture has been designed to support the family
of IBM PowerPC processors (PowerPC 601, 604 and 620).
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Link
to Cristina Silvano's Publications
Link
to Cristina Silvano on DBLP
Research
Projects
She
participated to a number of national and international research projects.
She is currently the European Coordinator of the project FP7-2PARMA-248716
on "PARallel PAradigms and Run-time MAnagement techniques for Many-core
Architectures" (Jan. 2010 - Dec. 2012). The 2PARMA Consortium is composed
of seven partners: Politecnico di Milano (Italy), STMicroelectronics (Italy and
France),
Heinrich Hertz Institute - Fraunhofer Institute for Telecommunications
(Germany), IMEC (Belgium), ICCS - Institute of Communication and Computer
Systems (Greece), RWTH Aachen University (Germany), Synopsys (Belgium). The
2PARMA project focuses on the definition of a parallel programming model
combining component-based and single-instruction multiple-thread approaches,
instruction set virtualisation based on portable bytecode, run-time resource
management policies and design space exploration
methodologies for Many-core Computing Fabrics.
She is currently participating to the ARTEMIS
SMECY Project on "Smart Multicore Embedded Systems" (start date:
01/02/2010). The SMECY project includes 30 partners from 9 European countries
(among others we can cite STMicroelectronics and Thales). Project
Coordinator: Francois Pacull (CEA, France).
She
was the European Coordinator of the project
FP7-MULTICUBE-216693 on "Multi-objective design space exploration
of multi-processor SoC architectures for embedded multimedia
applications" (Jan. 2008 - June 2010). The MULTICUBE Consortium
was composed of nine partners: Politecnico di Milano (Italy), Design of Systems
on Silicon – DS2 (Spain), STMicroelectronics
(Italy), IMEC (Belgium), ESTECO (Italy),
University of Lugano - ALaRI (Switzerland), University of Cantabria (Spain),
STMicroelectronics Beijing (China), Institute of Computing Technology –
Chinese Academy of Sciences (China).
In
the context of the MULTICUBE project, she is currently leading a research group at Politecnico di Milano whose research focuses on
design space exploration for multi-processor architectures working on an
open-source tool (MULTICUBE
Explorer) to enable an automatic and fast optimization of configurable
system architectures towards a set of objective functions such as energy and
delay. MULTICUBE Explorer provides a set of innovative sampling and
optimization techniques to help finding the multi-objective Pareto points. It also provides an open XML interface for supporting
exploration of new platforms/architectures by interacting with a
system-level simulator.
From
2005 to 2008, she collaborated with ALaRI-Advanced Learning and Research
Institute, part of the Faculty of Informatics of the University of Lugano (CH)
to the research and management activities of the European Research Project MEDEA+
LoMoSA+ (2A708): "Low-power
expertise for Mobile & multi-media System Applications". This
research activity on low-power Network-on-Chip architectures has been done in
collaboration with NXP (NL) and STMicroelectronics
(Grenoble, F).
In
the past, she
was also principal investigator in a number of industrial funded
research projects. Among them, she was principal investigator in the 2-year research contract: "Low
Power Network on Chip and Multiprocessor Platforms" (2006) in collaboration with Advanced System
Technology Division of STMicroelectronics. Previously, she was
principal investigator in the 2-year research contract:
“Low Power Network on Chip and Embedded
Architectures”(2003) in collaboration with AST Division of
STMicroeletctronics.
Recent
International Talks and Seminars
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April 7th, 2011,
"2PARMA
Project: PARallel PAradigms and Run-time MAnagement techniques for Many-core
Architectures", HIPEAC Cluster Meeting on Multi-core Architectures, 2011
Chamonix (F), Host: Per Stenström, Professor, Chalmers University of
Technology, Sweden. |
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November 24th, 2010,
"Automatic Design Space
Exploration for Chip Multi-processors", Workshop on "Challenges in
Embedded System Design": Involvement of SMEs in Designing Complex Systems (CMM
2010), University of Lugano, Switzerland, Workshop Organizers: G. De
Micheli (EPFL) and M. Sami (USI-Politecnico di Milano). |
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July 6th, 2010,
"MULTICUBE:
Multi-Objective Design Space Exploration of Multi-Core Architectures",
Research Projects Workshop at
ISVLSI 2010: IEEE
Computer Society Annual Symposium on VLSI, July 5-7, 2010, Lixouri Kefalonia,
Greece. |
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June
18th, 2010, at 11:00 am, Seminar at Department of Computer Science & Engineering, University of California, Riverside, CA,
USA, "Automatic Design Space Exploration for Chip-Multi Processors"
(Slides). Host: Walid Najjar, Professor, Computer Science and Engineering, University of California Riverside. |
| June
17th, 2010, at 11:00 am, Seminar at Department of Computer Science & Engineering, University of California,
Irvine, CA, USA, "Automatic Design Space Exploration for Chip-Multi Processors"
(Slides). Host: Alexander V. Veidenbaum, Professor, Dept. of Computer Science, University of California
Irvine. |
| March
23th, 2010, at 10:30 am in Room HB 16.140, Delft Technical University, Computer
Engineering Colloquium Series. Title of the talk: "A
Design Space Exploration Framework for Run-Time Resource Management on
Multi-Core Architectures" (Slides). Host: Prof. Koen
Bertels, Delft Technical University (NL). |
|
December
17, 2009, 11:15-12:00, Location: 3B00, NEC Laboratories America, Inc.,
Princeton Campus, Princeton (NJ - USA), Title of the talk: "Automatic
Design Space Exploration for Chip-Multi Processors". Host: Dr.
Marcello Lajolo (NEC Laboratories America). |
|
December
16, 2009, 4:45pm, E-Quad, B327, Princeton University, Department of
Electrical Engineering, Computer Engineering Seminar, Title of the Seminar: "Automatic
Design Space Exploration for Chip-Multi Processors", Host: Prof.
Ruby Lee, Princeton University. (Announcement). |
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July
29th, 2009, 11am-12pm PT Location: Kappa, 1U, HP Labs, Palo Alto, Title of
the talk: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques
to Automate Design Space Exploration for CMPs", Host: Dr. Matteo
Monchiero (Exascale Computing Lab, HP Labs, Palo Alto). |
| May
14th,2009, at 16h00 in Room HB 16.140, Delft Technical University, Computer
Engineering Colloquium Series. Title of the talk: "MULTICUBE
Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space
Exploration for CMPs" (Slides).
Host: Prof. Koen Bertels, Delft Technical University (NL). |
Link to Scientific
Services
Reviewer
Services
In
2010 and 2011, she has been called from the European Commission as Independent Expert to
evaluate proposals submitted to the FET-Open programme on FP7-ICT-2009 Information and
Communication
Technologies. In 2010, she has been called as Reviewer of research proposals
submitted to Programme Blanc International Edition 2010, ANR (Agence
Nationale de la Recherche), France. From
2005 to 2008, she has been called from the European Commission as
Independent Expert to review the Network-of-Excellence project FP6 - IST-4408
HiPEAC
(High-Performance Embedded Architectures and Compilers). In April 2005, she
has been called from the European Commission as
Independent Expert to evaluate project proposals submitted to the IV
Call IST (Information Society Technology) - FP6 (6th Framework Programme) on
Nanoelectronics. In 2007, she has been called as Primary Evaluator
for research projects at
INRIA (French National Institute for Computer Science,- France). In 2008 she has been
invited as Member of the Review Panel for Computer Science, Academy of Finland, Research Council for Natural
Sciences and Engineering. In 2009 she has been invited as Chair of the
same review panel.
Link to Teaching Activity
PAST
Ph.D. STUDENTS at Politecnico di Milano:
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VITTORIO
ZACCARIA, Ph. D., currently Assistant Professor at Dipartimento di Elettronica e
Informazione, Politecnico di Milano. System Architectures Group, and
previously R&D Engineer at STMicroelectronics,
Ph.D. Thesis on: "Power exploration
methodologies for VLIW-based systems", XIV, 2002, Advisor: prof. M. Sami.
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|
GIANLUCA
PALERMO, Ph.D., currently Assistant Professor at Dipartimento di Elettronica e
Informazione, Politecnico di Milano. System Architectures Group.
Ph.D. Thesis on: "Design
Methodologies for Embedded Architectures Based on Network on-Chip",
XVIII, Feb. 2006, Advisor: prof. C. Silvano
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MATTEO
MONCHIERO, Ph.D.,
currently
Senior Research Scientist,
Intel Labs and previously Post
Doctoral Research Associate at HP Labs in Palo Alto, CA, Exascale
Computing Lab.,
Ph.D. Thesis on: “Power/performance
analysis and optimization of multicore architectures”, XIX, Feb.
2007, Advisor: prof. C. Silvano
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ORESTE
VILLA,
Ph.D., currently Research Scientist in the High Performance Computing Group
at Pacific Northwest National Laboratory (www.pnl.gov),
Richland, WA (USA)
Ph.D. Thesis: “Designing
and Programming Multi-core Architectures”, XX, Feb. 2008, Advisor:
prof. C. Silvano
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OTHER
PReSENt/past Ph.D. STUDENTS and RESEARCH COLLABORATORS:
| GIOVANNI
AGOSTA, Ph. D., currently Assistant Professor at Dipartimento di Elettronica e
Informazione, Politecnico di Milano. Formal Languages and Compilers Group. His current research focuses on Dynamic
Compilation for ILP Architectures. The research advisor is Professor Stefano
Crespi Reghizzi, Politecnico di Milano. |
|
GIOVANNI
BELTRAME, Ph. D., currently Research Fellow at European Space Agency, The Hague Area, NL.
Ph.D. Thesis on: "Analysis and Optimization of Multi-Processor
System-on-Chip Platforms", XVIII, Feb. 2006, Politecnico di Milano,
Advisor: prof. D. Sciuto. |
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CAROLINE CONCATTO, Ph. D. student at Universidade Federal do Rio Grande
do Sul, Instituto de Informática, Departamento de Informática Aplicada,
Porto Alegre (Brasil). Advisor: Prof. Luigi Carro. |
| LEANDRO
FIORIN, Ph.D.
student at ALaRI, the Advanced Learning and Research Institute, part of
the Faculty of Informatics of the University of Lugano (Switzerland), Advisor:
prof. M. Sami.
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| GIOVANNI
MARIANI, Ph. D., currently Post-Doc at ALaRI, the Advanced Learning and Research Institute, part of
the Faculty of Informatics of the University of Lugano (Switzerland),
Ph.D. Thesis: "A Design Space Exploration Methodology Supporting Run-time
Resource Management for Multi-Core Architectures", Advisor:
prof. M. Sami, Co-Advisor: prof. C. Silvano
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EDOARDO PAONE,
Ph. D. student, Dipartimento di Elettronica e Informazione, Politecnico di
Milano. |
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SOTIRIOS XYDIS,
Ph. D. from Technical University of Athens, currently Post-Doc at
Dipartimento di Elettronica e Informazione, Politecnico di Milano.
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