|
| | CRISTINA
SILVANO - SHORT CV
She is an Associate Professor (with tenure) in Computer Engineering at Politecnico di
Milano, Department of Electronics and Computer Engineering, System
Architectures Group. Her
current primary research interests are in the area of
Computer Architectures and Electronic Design Automation, with particular emphasis on
design space exploration techniques and low-power design techniques for
multi-processor systems-on-chip. She is co-author of more than seventy
scientific papers
on international journals and conferences, collecting one best paper award. She
was co-author of the book: "Power Estimation and Optimization Methodologies for
VLIW-Based Embedded Systems", published
by Kluwer Academic Publisher (2003). She is co-editor of the books:
"Low-Power Networks-on-Chip" to be published by Kluwer Academic
Publisher (2010) and "Multi-objective design space exploration of
multiprocessor SoC architectures: the MULTICUBE approach" to be published by Kluwer Academic
Publisher (2011) . She holds two international patents
and she was co-inventor in five international patents
and in two pending international patents. She is Senior Member of IEEE and
Member of HiPEAC Network of
Excellence.
Education
She
received her Laurea Degree (M. Sc.) in Electronic Engineering
from Politecnico di Milano (Italy) in 1987 and her Ph. D. Degree in
Computer Engineering from University of
Brescia (Italy) on
March 1999 (XI) - Ph.D. Thesis title: “Power
Estimation and Optimization Methodologies for Digital Circuits and
Systems”.
Career
 | From
September 2002 to present, she is an Associate Professor (with tenure) in
Computer
Engineering at Politecnico di Milano, V
School of Engineering, Dipartimento di Elettronica e Informazione. Her
current primary research interests are in the area of
Computer Architectures and Electronic Design Automation, with particular emphasis on
design space exploration techniques and low-power design techniques for
multi-processor systems-on-chip. From
2005, she is also
collaborating with ALaRI-Advanced Learning and Research
Institute, part of the Faculty of Informatics of the University of Lugano (CH).
|
| From
October 2000 to September 2002, she was Assistant Professor in Computer Science at
University of Milan, School of
Mathematical Physical and Natural Sciences, Department
of Computer Science.
|
| From
September 1999 to September 2000, she was Post-Doctoral Researcher at the Dipartimento di Elettronica e
Informazione, Politecnico di Milano. Her research
activities were mainly related to the research contract: “Power
estimation methodologies for VLIW
architectures”, in collaboration with the Advanced
System Technology Division of ST Microelectronics. The
research activity carried out aimed at defining a power estimation and
optimization methodology for VLIW (Very Long Instruction Word) architectures
based on the Lx/ST200
family of VLIW embedded processor cores (developed as a partnership
between HP Labs and STMicroelectronics). The ST200 family (including the
ST210, ST220, ST231 processor cores) is used today for embedded media
processing in a variety of audio, video and imaging consumer
products.
|
| From
November 1998 to August 1999, she was a Consultant Researcher in the
Electronic Design Automation Area at CEFRIEL (Center for the Research and
the Education in Information Engineering) in Milan. The research activity
carried out aims at defining a more general HW/SW co-design environment for
control dominated embedded systems. This work is part of the co-design
project named TOSCA (Tools for System Co-design Automation) and the European
Project No. 26796 PEOPLE (Power Estimation for fast exPLoration of Embedded
systems).
|
| From
March 1996 to October 1998, she was with the Dipartimento di Elettronica per
l’Automazione, Università degli Studi di Brescia (Italy), where she was
pursuing her Ph. D. Degree in
Computer Engineering. She
received the Ph. D. Degree on
March 1999 discussing her thesis titled: “Power
Estimation and Optimization Methodologies for Digital Circuits and
Systems”. (Advisor:
Prof. P. Gubian, Università degli
Studi di Brescia, Co-advisor: Prof. D. Sciuto, Politecnico di Milano).
|
| From
May 1987 to February 1996, she was with Groupe
Bull (also known as Bull HN Information Systems), where
she held the position of Senior
Design Engineer in the ASIC Development and Validation Group,
Research & Development Labs in Pregnana M. (Italy). She participated in the
design of several VLSI circuits for Bull computer systems. She has also been
involved in the definition of design and
simulation methodologies at the system-level. From 1992, she was part of the
Bull - IBM (Austin-USA) team for the design of the first multiprocessor
systems based on PowerPC processor architecture. These systems have been
fully designed in the Bull R&D Labs in Italy and then commercialized as
Bull Escala Servers and IBM RS/6000 Symmetric Multiprocessor
Servers. These
shared-memory multiprocessor systems are symmetric and scalable up to
eight processors. The architecture has been designed to support the family
of IBM PowerPC processors (PowerPC 601, 604 and 620).
|
Link
to Cristina Silvano's Publications
Link
to Cristina Silvano on DBLP
Research
Projects
She
participated to a number of national and international research projects.
She is currently the European Coordinator of the project FP7-2PARMA-248716
on "PARallel PAradigms and Run-time MAnagement techniques for Many-core
Architectures" (Jan. 2010 - Dec. 2012). The 2PARMA Consortium is composed
of seven partners: Politecnico di Milano (Italy), STMicroelectronics (Italy),
Heinrich Hertz Institute - Fraunhofer Institute for Telecommunications
(Germany), IMEC (Belgium), ICCS - Institute of Communication and Computer
Systems (Greece), RWTH Aachen University (Germany), CoWare (Belgium). The
2PARMA project focuses on the definition of a parallel programming model
combining component-based and single-instruction multiple-thread approaches,
instruction set virtualisation based on portable bytecode, run-time resource
management policies and mechanisms as well as design space exploration
methodologies for Many-core Computing Fabrics.
She
is also the European Coordinator of the on-going
project
FP7-MULTICUBE-216693 on "Multi-objective design space exploration
of multi-processor SoC architectures for embedded multimedia
applications" (Jan. 2008 - June 2010). The MULTICUBE Consortium
is composed of nine partners: Politecnico di Milano (Italy), Design of Systems
on Silicon – DS2 (Spain), STMicroelectronics
(Italy), IMEC (Belgium), ESTECO (Italy),
University of Lugano - ALaRI (Switzerland), University of Cantabria (Spain),
STMicroelectronics Beijing (China), Institute of Computing Technology –
Chinese Academy of Sciences (China).
In
the context of the MULTICUBE project, she is
also currently leading a research group at Politecnico di Milano whose research focuses on
design space exploration for multi-processor architectures working on an
open-source tool (MULTICUBE
Explorer) to enable an automatic and fast optimization of configurable
system architectures towards a set of objective functions such as energy and
delay. MULTICUBE Explorer provides a set of innovative sampling and
optimization techniques to help finding the multi-objective Pareto points. It also provides an open XML interface for supporting
exploration of new platforms/architectures by interacting with a
system-level simulator.
From
2005 to 2008, she collaborated with ALaRI-Advanced Learning and Research
Institute, part of the Faculty of Informatics of the University of Lugano (CH)
to the research and management activities of the European Research Project MEDEA+
LoMoSA+ (2A708): "Low-power
expertise for Mobile & multi-media System Applications". This
research activity on low-power Network-on-Chip architectures has been done in
collaboration with NXP (NL) and STMicroelectronics
(Grenoble, F).
In
the past, she
was also principal investigator in a number of industrial funded
research projects. Among them, she was principal investigator in the 2-year research contract: "Low
Power Network on Chip and Multiprocessor Platforms" (2006) in collaboration with Advanced System
Technology Division of STMicroelectronics. Previously, she was
principal investigator in the 2-year research contract:
“Low Power Network on Chip and Embedded
Architectures”(2003) in collaboration with AST Division of
STMicroeletctronics.
Recent
International Talks and Seminars
|
December
17, 2009, 11:15-12:00, Location: 3B00, NEC Laboratories America, Inc.,
Princeton Campus, Princeton (NJ - USA), Title of the talk: "Automatic
Design Space Exploration for Chip-Multi Processors". Host: Dr.
Marcello Lajolo (NEC Laboratories America). |
|
December
16, 2009, 4:45pm, E-Quad, B327, Princeton University, Department of
Electrical Engineering, Computer Engineering Seminar, Title of the Seminar: "Automatic
Design Space Exploration for Chip-Multi Processors", Host: Prof.
Ruby Lee, Princeton University. (Announcement). |
|
July
29th, 2009, 11am-12pm PT Location: Kappa, 1U, HP Labs, Palo Alto, Title of
the talk: "MULTICUBE Explorer: Leveraging DoE/RSM-based Techniques
to Automate Design Space Exploration for CMPs", Host: Dr. Matteo
Monchiero (Exascale Computing Lab, HP Labs, Palo Alto). |
|
May
14th,2009, at 16h00 in Room HB 16.140, Delft Technical University, Computer
Engineering Colloquium Series. Title of the talk: "MULTICUBE
Explorer: Leveraging DoE/RSM-based Techniques to Automate Design Space
Exploration for CMPs" (Slides).
Host: Prof. Koen Bertels, Delft Technical University. |
Service
Activities
She
is an active member of the
computing and embedded system design community, and she regularly serves in
several international program and organization committees.
-
MICRO-41,
the 41st Annual IEEE/ACM International Symposium on Microarchitecture, Como
(Italy), 2008, General Co-Chair
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MICRO-43,
the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, Atlanta
(US), 2010, TPC Member
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SASP,
IEEE Symposium on Application Specific Processors (Co-located with ACM/IEEE
Design Automation Conference), Publicity Chair 2008,
General Co-Chair 2009, Program Co-Chair 2010
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WASP:
Workshop on Application Specific Processors, TPC
Member (2004, 2005), Publicity Chair 2007
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WS-SAMOS
IX Workshop on
Systems, Architectures, Modeling and Simulation, Program Co-Chair 2009
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IC-SAMOS
: International
Conference on Systems, Architectures, Modeling, and Simulation, TPC Member
(2006, 2007, 2008)
-
DATE:
IEEE/ACM Design and Test in Europe Conference, "Power Estimation and
Optimization" Track. TPC Member (2005 - present)
-
Co-Organizer and Architectures Session Chair of DATE
2010 Friday Workshop on Designing for Embedded Parallel Computing
Platforms: Architectures, Design Tools, and Applications
-
Co-Organizer and Architectures Session Chair of DATE
2009 Friday Workshop on Designing for Embedded Parallel Computing
Platforms: Architectures, Design Tools, and Applications
-
General Co-Chair of PARMA
Workshop on Parallel Programming and Run-time Management Techniques
for Many-core Architectures - co-located with ARCS
2010 - Architecture of Computing Systems Conference
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NOCS:
ACM/IEEE International Symposium on Networks-on-Chip, TPC Member (2009,
2010)
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HiPEAC International
conference on High-Performance Embedded Architectures and Compilers, TPC
member 2010.
-
Co-Organizer of 2nd Workshop on: Rapid Simulation and Performance
Evaluation: Methods and Tools (RAPIDO‘2010)
co-located with HiPEAC
2010
-
WRC 2010 4th
HiPEAC Workshop on Reconfigurable Computing, TPC member 2010
-
VLSI-SoC: IFIP/IEEE International Conference 16th International Conference on Very
Large Scale Integration, TPC Member (2008, 2009, 2010)
-
ICS:
The 20th ACM International Conference on Supercomputing, TPC
Member 2006.
-
DAC:
ACM/IEEE Design Automation Conference, Reviewer (2004-2007)
She
was a Reviewer for several international journals such as IEEE Transactions on
Computers, IEEE Transactions on VLSI Systems, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, IEEE Design and Test,
ACM Transactions on Design Automation of Electronic Systems, Journal of VLSI
Signal Processing Systems- Springer, EURASIP Journal on Embedded Systems –
Hindawi Publishing Corporation.
From 2003 to 2005 she
was Associate Editor of JSA: Journal of Systems Architecture - The Euromicro
Journal, Elsevier.
Reviewer
Services
From
2005 to 2008, she has been called from the European Commission as
Independent Expert to review the Network-of-Excellence project FP6 - IST-4408
HiPEAC
(High-Performance Embedded Architectures and Compilers). In April 2005, she
has been called from the European Commission as
Independent Expert to evaluate project proposals submitted to the IV
Call IST (Information Society Technology) - FP6 (6th Framework Programme) on
Nanoelectronics. In 2007, she has been called as Primary Evaluator of the
INRIA (French National Institute for Computer Science,- France) for the research
project MODSIM (MODular SIMulation) carried out by INRIA - Futurs and
Computer Science Department, Princeton University (USA). In 2008 she has been
invited as Member of the Review Panel for Computer Science, Academy of Finland, Research Council for Natural
Sciences and Engineering. In 2009 she has been invited as Chair of the
same review panel. In May 2009, she has been invited as Opponent Member of the Doctoral
Examination Committee, Board of the Doctorates, Delft University of Technology
(NL) for the Ph.D. defense of the candidate Carlo Galuzzi discussing a
thesis titled: "Automatically fused instructions".
Recent
Teaching Activity (from 2002-2003 to 2009-2010)
Since
the academic year 1998/99 she has been lecturing, first as an assistant later
as the course lecturer at University of Milan and Politecnico di Milano, in
various courses. Among the most recent Academic Courses, we can cite:
2009-2010
"Architectures for multimedia systems", Master of Science, Computer
Engineering, Politecnico di Milano, Campus Como.
"Computer Architectures and Operating Systems", Undergraduate
Programme, Computer
Engineering, Politecnico di Milano, Campus Como.
2008-2009
"Architectures for multimedia systems", Master of Science, Computer
Engineering, Politecnico di Milano, Campus Como.
"HW/SW Co-Design", Master of Science, Computing Systems Engineering,
Politecnico di Milano, Campus Milano Leonardo.
2007-2008
"Architectures for multimedia systems", Master of Science, Computer
Engineering, Politecnico di Milano, Campus Como.
"HW/SW Co-Design", Master of Science, Computing Systems Engineering,
Politecnico di Milano, Campus Milano Leonardo.
"Computer Science Fundamentals", Undergraduate Programme, Management
and Production Engineering, Politecnico di Milano, Campus Como.
2006-2007
"Architectures for multimedia systems", Master of Science, Computer
Engineering, Politecnico di Milano, Campus Como.
"HW/SW Co-Design", Master of Science, Computing Systems Engineering,
Politecnico di Milano, Campus Milano Leonardo.
"Computer Science Fundamentals", Undergraduate Programme, Management
and Production Engineering, Politecnico di Milano, Campus Como.
"Computer Architectures", Undergraduate Programme, Information and
Communication technology, University of Milan
"Advanced Computer Architectures", Ph. D. programme, Computing Systems
Engineering, Politecnico di Milano, Campus Milano Leonardo (in collaboration
with prof. M. Sami)
2005-2006
"Architectures for multimedia systems", Master of Science, Computer
Engineering, Politecnico di Milano, Campus Como.
"HW/SW Co-Design", Master of Science, Computing Systems Engineering,
Politecnico di Milano, Campus Milano Leonardo.
"Computer Science Fundamentals", Undergraduate Programme, Management
and Production Engineering, Politecnico di Milano, Campus Como.
"Computer Architectures", Undergraduate Programme, Information and
Communication technology, University of Milan
2004-2005
"Architectures for multimedia systems", Master of Science, Computer
Engineering, Politecnico di Milano, Campus Como.
"HW/SW Co-Design", Master of Science, Computing Systems Engineering,
Politecnico di Milano, Campus Milano Leonardo.
"Computer Science Fundamentals", Undergraduate Programme, Management
and Production Engineering, Politecnico di Milano, Campus Como.
"Computer Architectures", Undergraduate Programme, Information and
Communication technology, University of Milan
2003-2004
"Architectures for multimedia systems", Master of Science, Computer
Engineering, Politecnico di Milano, Campus Como.
"Computer Science Fundamentals", Undergraduate Programme, Management
and Production Engineering, Politecnico di Milano, Campus Como.
"Computer Architectures", Undergraduate Programme, Information and
Communication technology, University of Milan
2002-2003
"Computer Architectures", Master of Science, Electronic and
Communication Engineering, Politecnico di Milano, Campus Leonardo.
"Computer Science Fundamentals", Undergraduate Programme, Management
and Production Engineering, Politecnico di Milano, Campus Como.
"Computer Architectures", Undergraduate Programme, Information and
Communication technology, University of Milan
PAST
Ph.D. STUDENTS at Politecnico di Milano:
|
VITTORIO
ZACCARIA, Ph. D., currently Research Associate at Dipartimento di Elettronica e
Informazione, Politecnico di Milano. System Architectures Group.
Ph.D. Thesis on: "Power exploration
methodologies
|
|
GIANLUCA
PALERMO, Ph.D., currently Assistant Professor at Dipartimento di Elettronica e
Informazione, Politecnico di Milano. System Architectures Group.
Ph.D. Thesis on: "Design
Methodologies for Embedded Architectures Based on Network on-Chip",
XVIII, Feb. 2006, Advisor: prof. C. Silvano
|
|
MATTEO
MONCHIERO, Ph.D.,
currently
Post
Doctoral Research Associate at HP Labs in Palo Alto, CA, Exascale
Computing Lab.
Ph.D. Thesis on: “Power/performance
analysis and optimization of multicore architectures”, XIX, Feb.
2007, Advisor: prof. C. Silvano
|
|
ORESTE
VILLA,
Ph.D., currently Research Scientist in the High Performance Computing Group
at Pacific Northwest National Laboratory (www.pnl.gov),
Richland, WA (USA)
Ph.D. Thesis: “Designing
and Programming Multi-core Architectures”, XX, Feb. 2008, Advisor:
prof. C. Silvano
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OTHER
PReSENt/past Ph.D. STUDENTS and RESEARCH COLLABORATORS:
| GIOVANNI
AGOSTA, Ph. D., currently Assistant Professor at Dipartimento di Elettronica e
Informazione, Politecnico di Milano. Formal Languages and Compilers Group. His current research focuses on Dynamic
Compilation for ILP Architectures. The research advisor is Professor Stefano
Crespi Reghizzi, Politecnico di Milano.
|
|
GIOVANNI
BELTRAME, Ph. D., currently Research Fellow at European Space Agency, The Hague Area, NL.
Ph.D. Thesis on: "Analysis and Optimization of Multi-Processor
System-on-Chip Platforms", XVIII, Feb. 2006, Politecnico di Milano,
Advisor: prof. D. Sciuto.
|
| LEANDRO
FIORIN, Ph.D.
student at ALaRI, the Advanced Learning and Research Institute, part of
the Faculty of Informatics of the University of Lugano (Switzerland), Advisor:
prof. M. Sami.
|
| GIOVANNI
MARIANI, Ph. D. student at ALaRI, the Advanced Learning and Research Institute, part of
the Faculty of Informatics of the University of Lugano (Switzerland), Advisor:
prof. M. Sami.
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| FABRIZIO
CASTRO, Ph.
D. student, Dipartimento di Elettronica e Informazione, Politecnico di
Milano.
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| CAROLINE
CONCATTO, Ph. D. student at Universidade Federal do Rio Grande do Sul,
Instituto de Informática, Departamento de Informática Aplicada, Porto
Alegre (Brasil). Advisor: Prof. Luigi Carro.
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