|
|
Title |
Publication number |
Publication date |
Inventor(s) |
Applicant(s) |
Application number |
Date of application |
|
1 |
Integrated CMOS static RAM.
|
EP0578900 (A1) |
1994-01-19
|
SADA GIANCARLO [IT]
SILVANO CRISTINA [IT]
|
BULL HN INFORMATION SYST [IT]
|
EP19920830383
|
1992-07-16
|
|
|
|
EP0578900 (B1) |
1997-11-05
|
|
|
|
|
|
2 |
Integrated CMOS static RAM.
|
DE69223046 (T2) |
1998-02-26
|
SADA GIANCARLO [IT]
SILVANO CRISTINA [IT]
|
BULL HN INFORMATION SYST [IT]
|
DE19926023046T
|
1992-07-16
|
|
3 |
Digital information error correcting apparatus for single error
correcting (SEC), double error detecting (DED), single byte error
detecting (SBED), and odd numbered single byte error correcting (OSBEC)
|
US5535227 (A) |
1996-07-09
|
SILVANO CRISTINA [IT]
|
BULL HN INFORMATION SYST [IT]
|
US19940248140
|
1994-05-23
|
|
4 |
Digital information error correcting apparatus for correcting single
errors(sec),detecting double errors(ded)and single byte multiple errors(sbd),and
the correction of an odd number of single byte errors(odd sbc).
|
EP0629051 (A1) |
1994-12-14
|
SILVANO CHRISTINA [IT]
|
BULL HN INFORMATION SYST [IT]
|
EP19930830254
|
1993-06-10
|
|
|
|
EP0629051 (B1) |
1998-04-01
|
|
|
|
|
|
5 |
Digital information error correcting apparatus for correcting single
errors(sec),detecting double errors(ded)and single byte multiple errors(sbd),and
the correction of an odd number of single byte errors(odd sbc).
|
DE69317766 (T2) |
1998-07-30
|
SILVANO CHRISTINA [IT]
|
BULL HN INFORMATION SYST [IT]
|
DE19936017766T
|
1993-06-10
|
|
6 |
Encoder/decoder architecture and related processing system
|
US2002019896 (A1) |
2002-02-14
|
FORNACIARI WILLIAM [IT]
SCIUTO DONATELLA [IT]
SILVANO CRISTINA [IT]
ZAFALON ROBERTO [IT]
PAU DANILO [IT]
|
FORNACIARI WILLIAM,
SCIUTO DONATELLA,
SILVANO CRISTINA,
ZAFALON ROBERTO,
PAU DANILO
|
US20010843533
|
2001-04-25
|
|
7 |
Encoder architecture for parallel busses
|
EP1150467 (A1) |
2001-10-31
|
FORNACIARI WILLIAM [IT]
SCIUTO DONATELLA [IT]
SILVANO CHRISTINA [IT]
ZAFALON ROBERTO [IT]
PAU DANILO [IT]
|
ST MICROELECTRONICS SRL [IT]
|
EP20000830322
|
2000-04-28
|
|
8 |
Processor architecture
|
US2002124155 (A1) |
2002-09-05
|
SAMI MARIAGIOVANNA [IT]
SCIUTO DONATELLA [IT]
SILVANO CRISTINA [IT]
ZACCARIA VITTORIO [IT]
PAU DANILO [IT]
ZAFALON ROBERTO [IT]
|
ST MICROELECTRONICS SRL [IT]
|
US20010976241
|
2001-10-11
|
|
|
|
US6889317 (B2) |
2000-10-17
|
|
|
|
|
|
9 |
Processor architecture with variable-stage pipeline
|
EP1199629 (A1) |
2002-04-24
|
SAMI MARIAGIOVANNA [IT]
SCIUTO DONATELLA [IT]
SILVANO CRISTINA [IT]
ZACCARIA VITTORIO [IT]
PAU DANILO [IT]
ZAFALON ROBERTO [IT]
|
ST MICROELECTRONICS SRL [IT]
|
EP20000830673
|
2000-10-17
|
|
10 |
PROGRAMMABLE DATA PROTECTION DEVICE, SECURE PROGRAMMING MANAGER SYSTEM
AND PROCESS FOR CONTROLLING ACCESS TO AN INTERCONNECT NETWORK FOR AN
INTEGRATED CIRCUIT
|
US2009089861 (A1) |
2009-04-02
|
CATALANO VALERIO [FR]
COPPOLA MARCELLO [FR]
LOCATELLI RICCARDO [FR]
SILVANO CRISTINA [IT]
PALERMO GIANLUCA [IT]
FIORIN LEANDRO [CH]
|
STMICROELECTRONICS GRENOBLE SA [FR]
|
US20080207131
|
2008-09-09
|
|
11 |
Programmable data protection device, secure programming manager system
and process for controlling access to an interconnect network for an
integrated circuit.
|
EP2043324 (A1) |
2009-04-01
|
CATALANO VALERIO [FR]
COPPOLA MARCELLO [FR]
LOCATELLI RICCARDO [FR]
SILVANO CRISTINA [IT]
PALERMO GIANLUCA [IT]
FIORIN LEANDRO [CH]
|
STMICROELECTRONICS GRENOBLE SA [FR]
|
EP20070301411
|
2007-09-28
|
