International Journals with peer review

1. Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, "OSCAR: an Optimization Methodology Exploiting Spatial Correlation in Multi-core Design Space", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Accepted for publication, 2011.

2. Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria.
   "A Variability-Aware Robust Design Space Exploration Methodology for CMPs",
   ACM Transactions on Embedded Computing Systems.  Vol. 10, Issue 4, August 2011, Accepted for publication.

3. Andrea Di Biagio, Giovanni Agosta, Cristina Silvano and Martino Sykora.
   "Architecture Optimization of Application-Specific Implicit Instructions".
   ACM Transactions on Embedded Computing Systems. Vol. 11, Accepted for publication.

4. Chantal Ykman-Couvreur, Prabhat Avasare, Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria.
   "Linking run-time resource management of embedded multi-core platforms with automated design-time exploration",
   IET Computers and Digital Techniques, March 2011, Vol. 5, Iss. 2, pp. 123-135.

5. Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria.
   "ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration",
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VOL. 28, NO. 12, DECEMBER 2009, pp. 1816-1829.

6. Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Valerio Catalano, Cristina Silvano,
   "Secure Memory Accesses on Networks-on-Chip",
   IEEE Transactions on Computers, Vol. 57, No. 9, pp. 1216-1229, Sept., 2008, ISSN: 0018-9340.

7. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano,
   "Multi-Accuracy Power and Performance Transaction-Level Modeling",
   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 26, No. 10 , October 2007, Pages: 1830 -1842.

8. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
   "Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors",
   Journal of Systems Architecture: The EUROMICRO Journal - Elsevier, Volume 53, Number 10, October 2007, pp. 719-732.

9. Cristina Silvano, Giovanni Agosta, Gianluca Palermo,
   "Efficient Architecture/Compiler Co-Exploration Using Analytical Models",
   Design Automation for Embedded Systems, Springer, Volume 11, Issue 1, March 2007, pp. 1-23, ISSN 0929-5585 (Print) 1572-8080 (Online).

10. A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon, 
    "Reducing the Complexity of Instruction-Level Power Models for VLIW Processors"
    Design Automation for Embedded Systems, Springer US, 19.07.2006, vol. 10, no. 1, pp. 49-67.

11. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa,
    "Efficient Synchronization for Embedded on-Chip Multiprocessors"
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 10, October 2006, pp. 1049-1062.

12. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa.
    "An Efficient Synchronization Technique for Multiprocessor Systems on-Chip",
    ACM SIGARCH Computer Architecture News, Volume 34 , Issue 1 (March 2006) pp. 33-40.

13. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria,
    "Multi-Objective Design Space Exploration of Embedded Systems",
    Journal of Embedded Computing, ISSN 1740-4460, 2005, Vol. 1, No. 3, IOS Press, pp. 305-316.

14. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria and Roberto Zafalon,
    “Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach”,
    Integration, The VLSI Journal, ELSEVIER, Volume 38, Issue 3, January 2005, pp. 515-524.

15. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria and R. Zafalon,
    “Low-Power Data Forwarding for VLIW Embedded Architectures”,
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 5, October 2002, Pages: 614 - 622.

16. Luca Benini, Davide Bruni, Mauro Chinosi, Cristina Silvano, Vittorio Zaccaria, and Roberto Zafalon,
    “A Framework for Modeling and Estimating the Energy Dissipation of VLIW-based Embedded Systems”,
    Design Automation for Embedded Systems, Kluwer Academic Publishers, Boston, October 2002, Volume 7, Issue 3, Pages:  183-203.

17. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria,
    “An Instruction-Level Energy Model for Embedded VLIW Architectures”,
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 21, Issue: 9 , Sept. 2002, Pages: 998 -1010.

18. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria,
    "A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems",
    Design Automation for Embedded Systems, Vol. Special Issue on "Design Methodologies and Tools for Real-Time Embedded Systems", Kluwer Academic Publishers, Boston, September 2202, Volume 7, Issue 1-2, Pages:  7-33.

19. Franco Fummi, Donatella Sciuto, Cristina Silvano,
    “Automatic Generation of Error Control Codes for Computer Applications”, 
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 6, No. 3, Sept. 1998, pp. 502-506.

20. William Fornaciari, Paolo Gubian, Donatella Sciuto, Cristina Silvano,
    “Power Estimation of Embedded Systems: a Hardware/Software Co-design Approach”, 
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.6, No. 2, Jun. 1998, pp.266-275.
    This work has been selected to be re-published in Chapter 3 of the book: “Readings in Hardware/Software Co-design”, edited by G. De Micheli, R. Ernst, and W. Wolf, The Morgan Kaufmann Series in Systems on Silicon, Jun. 2001, ISBN 1-55860-702-1.

21. William Fornaciari, Paolo Gubian, Donatella Sciuto, Cristina Silvano,
    “A VHDL-based Approach for Power Estimation of Embedded Systems”,
    Journal of System Architecture: The EUROMICRO Journal, Volume 44, Issue 1, October 1997, pp.37-61.

22. Luca Penzo, Donatella Sciuto, Cristina Silvano,
    “Construction Techniques for Systematic SEC-DED Codes with Single Byte Error Detection and Partial Correction Capability for Computer Memory Systems”, 
    IEEE Transactions on Information Theory, Vol. 41, No. 2, Mar. 1995, pp. 584-591.

International Books 

1. Vittorio Zaccaria, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano,
   "Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems",
   Kluwer Academic Publishers, Boston, Hardbound, ISBN 1-4020-7377-1,February 2003,  201 pp.
   Contents.

Chapters in International Books

1. Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martinez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Fan Dongrui, Zhang Hao and Tang Shibin, "MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures", pg. 47-63, in "VLSI 2010 Annual Symposium",  Selected Papers, Nikolaos Voros, Amar Mukherjee, Nicolas Sklavos, Konstantinos Masselos, Michael Huebner (Editors), Lecture Notes in Electrical Engineering, Volume 57, 1st Edition., 2011, VIII, 331 p., Springer Netherlands, ISBN 978-94-007-1487-8, Due: August 31, 2011.
    

2. C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Melpignano, J.-M. Zins, D. Siorpaes, H. Hübert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers, H. Meyr, J. Ansari, P. Mähönen and B. Vanthournout, "2PARMA: Parallel Paradigms and 3 Run-time Management Techniques for Many-Core Architectures", pg. 65-79, in "VLSI 2010 Annual Symposium", Selected Papers, Nikolaos Voros, Amar Mukherjee, Nicolas Sklavos, Konstantinos Masselos, Michael Huebner (Editors), Lecture Notes in Electrical Engineering, Volume 57, 1st Edition., 2011, VIII, 331 p., Springer Netherlands, ISBN 978-94-007-1487-8, Due: August 31, 2011.
    

3. Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martinez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Fan Dongrui, Zhang Hao, "The MULTICUBE Design Flow", pg 3-17, in  "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach", Cristina Silvano; William Fornaciari; Eugenio Villar; (Editors); Springer, 1st Edition., 2011, XVIII, 222 p., 88 illus. Hardcover, ISBN 978-1-4419-8836-2, Due: August 29, 2011.

4. Enrico Rigoni, Carlos Kavka, Alessandro Turco, Gianluca Palermo,Cristina Silvano, Vittorio Zaccaria, GiovanniMariani, "Optimization Algorithms for Design Space Exploration of Embedded Systems", pg 51-74, in  "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach", Cristina Silvano; William Fornaciari; Eugenio Villar; (Editors); Springer, 1st Edition., 2011, XVIII, 222 p., 88 illus. Hardcover, ISBN 978-1-4419-8836-2, Due: August 29, 2011.

5. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Enrico Rigoni,Carlos Kavka, Alessandro Turco and Giovanni Mariani, "Response Surface Modeling for Design Space Exploration of Embedded Systems", pg 75-92, in  "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach", Cristina Silvano; William Fornaciari; Eugenio Villar; (Editors); Springer, 1st Edition., 2011, XVIII, 222 p., 88 illus. Hardcover, ISBN 978-1-4419-8836-2, Due: August 29, 2011.

6. Prabhat Avasare, Chantal Ykman-Couvreur, Geert Vanmeerbeeck, Giovanni Mariani, Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria, "Design Space Exploration Supporting Run-Time Resource Management", pg 93-107, in  "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach", Cristina Silvano; William Fornaciari; Eugenio Villar; (Editors); Springer, 1st Edition., 2011, XVIII, 222 p., 88 illus. Hardcover, ISBN 978-1-4419-8836-2, Due: August 29, 2011.

7. Carlos Kavka, Luka Onesti, Enrico Rigoni, Alessandro Turco, Sara Bocchio, Fabrizio Castro, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria, Giovanni Mariani, Fan Dongrui, Zhang Hao, and Tang Shibin, "Design Space Exploration of Parallel Architectures", pg 171-188, in  "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach", Cristina Silvano; William Fornaciari; Eugenio Villar; (Editors); Springer, 1st Edition., 2011, XVIII, 222 p., 88 illus. Hardcover, ISBN 978-1-4419-8836-2, Due: August 29, 2011.

8. Giovanni Mariani, Chantal Ykman-Couvreur, Prabhat Avasare, Geert Vanmeerbeeck, Gianluca Palermo, Cristina Silvano and Vittorio
   Zaccaria, "Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming", pg 189-204, in  "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach", Cristina Silvano; William Fornaciari; Eugenio Villar; (Editors); Springer, 1st Edition., 2011, XVIII, 222 p., 88 illus. Hardcover, ISBN 978-1-4419-8836-2, Due: August 29, 2011.

9. Leandro Fiorin, Gianluca Palermo, Cristina Silvano, "Security in NoC", in "Networks-on-Chips: Theory and Practice". Fayez Gebali, Haytham Elmiligi, and M.Watheq El-Kharashi (Eds.), Taylor & Francis Group LLC - CRC Press, 2008, pg 157-194

10. Giovanni Beltrame, Donatella Sciuto, and Cristina Silvano, "A Power-Efficient Methodology for Mapping Applications on Multi-Processor System-On-Chip Architectures" ,
    VLSI-SoC: Research Trends in VLSI and Systems on Chip Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France, Series: IFIP International Federation for Information Processing , Vol. 249 De Micheli, Giovanni; Mir, Salvador; Reis, Ricardo (Eds.) 2008, 398 p., Hardcover ISBN: 978-0-387-74908-2, Springer Ed. 

11. L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, "Address Bus Encoding Techniques for System-Level Power Optimization", Design, Automation, and Test in Europe - The Most Influential Papers of 10 Years DATE Lauwereins, Rudy; Madsen, Jan (Eds.), 2008, Approx. 530 p., ISBN: 978-1-4020-6487-6, Springer Ed.

12. D. Barretta, L. Breveglieri, P. Maistri, M. Monchiero, L. Negri, A. Pagni,  G. Palermo, M. Sami, C. Silvano, O. Villa, R. Zafalon, "Low Power Architectures for Mobile Systems",
    in "Mobile Information Systems - Infrastructure and Design for Adaptivity and Flexibility". Barbara Pernici Editor, Springer Ed., 2006, pp 177-206.

13. W. Fornaciari , P. Gubian, D. Sciuto, C. Silvano, “Power Estimation of Embedded Systems: a Hardware/Software Co-design Approach”, “Readings in Hardware/Software Co-design”, Edited by  G. De Micheli, R. Ernst, e W. Wolf, The Morgan Kaufmann Series in Systems on Silicon, June, 2001, ISBN 1-55860-702-1.

Editorial Contributions

1. Silvano, Cristina; Fornaciari, William; Soudris, Dimitrios (Editors), "Run-time Management techniques for Many-core Architectures" , Springer, 1st Edition., 2013, 250 p., 75 illus., Hardcover, ISBN 978-1-4614-0955-7, Due: June 29, 2013

2. Cristina Silvano; William Fornaciari; Eugenio Villar; (Editors), "Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach", Springer, 1st Edition., 2011, XVIII, 222, p. 88 illus. Hardcover, ISBN 978-1-4419-8836-2, Due: August 29, 2011
    

3. Cristina Silvano; Marcello Lajolo; Gianluca Palermo; (Editors), "Low-Power Networks- on-Chip", Springer, 1st Edition., 2011, X, 300 p. 100 illus., Hardcover ISBN: 978-1-4419-6910-1

4. Mladen Berekovic; William Fornaciari; Uwe Brinkschulte; Cristina Silvano; (Editors.), "Architecture of Computing Systems - ARCS 2011", 24th International Conference, Lake Como, Italy, February 24-25, 2011. Proceedings, Springer, Series: Lecture Notes in Computer Science, Vol. 6566, Subseries: Theoretical Computer Science and General Issues, 1st Edition., 2011, XIII, 271 p., ISBN 978-3-642-19136-7

5. Koen Bertels; Nikita Dimopoulos; Cristina Silvano; Stephan Wong (Editors.), Embedded Computer Systems: Architectures, Modeling, and Simulation 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Springer Proceedings Series: Lecture Notes in Computer Science Subseries: Theoretical Computer Science and General Issues , Vol. 5657, 2009, XIV, 342 p., Softcover ISBN: 978-3-642-03137-3.

6. MICRO-41  2008 41st IEEE/ACM International Symposium on Microarchitecture, 2008, 8-12 Nov. 2008, Lake Como. (Content).

Academic Books (in Italian)

1. F. Fummi, M. Sami, C. Silvano, "Progettazione digitale" (in Italian) - Second Edition, McGraw-Hill, Jan 2007, ISBN: ISBN:  88-386-6352-1, 390p.

2. F. Fummi, M. Sami, C. Silvano, "Progettazione digitale", (in Italian), McGraw-Hill, Feb. 2002, ISBN 88-386-6027-1.
   Web site: www.ateneonline.it/fummi

International Conferences with peer review

1. Debora Matos, Gianluca Palermo, Vittorio Zaccaria, Cezar Reinbrecht, Altamiro Susin, Cristina Silvano and Luigi Carro, "Floorplanning-Aware Design Space Exploration for Application-Specific Hierarchical Networks on-Chip", In NoCArc'11 - Fourth International Workshop on Network on-Chip Architectures. To be held in conjunction with the 44th Annual IEEE/ACM Int. Symposium on Microarchitecture (MICRO-44) December 3-7, 2011 Porto Alegre, Brazil.

2. Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Kastensmidt, Gianluca Palermo and Cristina Silvano. "Two-levels of adaptive buffer for virtual channel router in NoCs", In Proceedings of IFIP VLSI-SoC 2011, International Conference on Very Large Scale Integration of System-on-Chip. Hong-Kong, October 2011, pp. XX-XX.

3. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "ARTE: an Application-specific Run-Time Management Framework for Multi-core Systems" In Proceedings IEEE SASP'11 - Symposium on Application Specific Processors, San Francisco, CA, USA, June 2011, pp. 86-93.

4. Leandro Fiorin, Gianluca Palermo, Cristina Silvano. "A Monitoring System for NoCs ", In NoCArc'10 - International Workshop on Network on-Chip Architectures. Atlanta, GA, USA, December 2010, pp. 25-30.

5. C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Huebert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers H. Meyr, J. Ansari, P. Mahonen, and B. Vanthournout " 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-core Architectures ",
   ISVLSI 2010: IEEE Annual Symposium on VLSI, pp. 494-499, Lixouri, Kefalonia - Greece, July 2010.

6. C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, M. Martinez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-Couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondi, G. Mariani, H. Posadas, E. Villar, C. Wu, F. Dongrui, Z. Hao, and T. Shibin "Multicube: Multi-objective design space exploration of multi-core architectures ",
   ISVLSI 2010: IEEE Annual Symposium on VLSI, pp. 488-493, Lixouri, Kefalonia - Greece, July 2010.

7. Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Aleksandar Brankovic, Jovana Jovic, Cristina Silvano. "A Correlation-Based Design Space Exploration Methodology for Multi-Processor Systems-on-Chip ",
   In DAC-47 - Design Automation Conference, Anaheim, CA, USA, June 2010, pp. 120-125. 

8. Giovanni Mariani, Vittorio Zaccaria, Gianluca Palermo, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Cristina Silvano. " An industrial design space exploration framework for supporting run-time resource management on multi-core systems ",
   In DATE 2010 - International Conference on Design, Automation and Test in Europe. Dresden, Germany. March 2010, pp. 196-201.

9. Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian Vintan, Cristina Silvano. " Energy-Performance Design Space Exploration of SMT Architectures Exploiting Selective Load Value Predictions ",
   In DATE 2010 - International Conference on Design, Automation and Test in Europe. Dresden, Germany. March 2010, pp. 271-274.

10. Vittorio Zaccaria, Gianluca Palermo, Giovanni Mariani, Fabrizio Castro, Cristina Silvano. "Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors ",
    In PARMA Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architectures. Hannover, Germany, February pp. 325-331.

11. Anirban Dutta Choudhury, Gianluca Palermo, Cristina Silvano and Vittorio Zaccaria. "Yield Enhancement by Robust Application-specific Mapping on Network-on-Chips ",
    In NoCArc'09 - Second International Workshop on Network on-Chip Architectures, co-located with MICRO42,  New York City, USA, December 2009, pp. 37-42.

12. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip ",
    In Euromicro Proceedings of DSD'09 - Conference on Digital System Design. Patras, Greece, August 2009, pp. 383-389.

13. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "A Design Space Exploration Methodology Supporting Run-Time Resource Management for Multi-Processors System on-Chip",
    In Proceedings IEEE SASP'09 - Symposium on Application Specific Processors, Co-located with DAC 2009, San Francisco, CA, USA, July 2009, pp. 21-28.

14. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "Multiprocessor System-on-Chip Design Space Exploration based on Multi-level Modeling Techniques",
    In Proceedings of IEEE IC-SAMOS'09 - International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July 2009, pp. 118-124.

15. Leandro Fiorin, Gianluca Palermo, Cristina Silvano. "MPSoCs Run-Time Monitoring through Networks-on-Chip",
    In DATE 2009 - International Conference on Design, Automation and Test in Europe. Nice, France. April 2009, pp. 558-561.

16. G. Palermo C. Silvano, V. Zaccaria, "Variability-Aware Robust Design Space Exploration of Chip Multiprocessor Architectures".
    In Proceedings of ASP-DAC 2009, 14th Asia and South Pacific Design Automation Conference. Yokohama, Japan, January 2009, pp. 323-328.

17. L. Fiorin, G. Palermo, C. Silvano, "A Security Monitoring Service for NoCs",
    In ACM Proceedings of CODES+ISSS 2008 - International Conference on Hardware-Software Codesign and System Synthesis. Atlanta, Georgia, USA, October 2008, pp. 197-2002.

18. G. Palermo, C. Silvano, V. Zaccaria, "Robust Optimization of SoC Architectures: A Multi-Scenario Approach",
    In Proceedings of ESTIMedia 2008 - IEEE Workshop on Embedded Systems for Real-Time Multimedia. Atlanta, Georgia, USA, October 2008, pp. 7-12. (PDF)

19. O. Villa, G. Palermo, C. Silvano, "Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures",
    In Proceedings of CASES 2008- International Conference on Compilers, Architectures and Synthesis for Embedded Systems. Atlanta, Georgia, USA, October 2008, pp. 81-90.
    

20. G. Mariani, G.Palermo, C. Silvano and V. Zaccaria, "An Efficient Design Space Exploration Methodology for Multi-Cluster VLIW Architectures based on Artificial Neural Networks",
    IFIP-VLSI-SOC 2008, 2008 IFIP International Conference on Very Large Scale Integration, 13-15 Oct. 2008, Rhodos (Greece).
    

21. G.Palermo, C. Silvano and V. Zaccaria, "Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration",
    Proceedings of 11th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2008,  2008, Sept. 2-5, Parma, Italy. 
      

22. M. Monchiero, G. Palermo, C. Silvano, O. Villa, "A Modular Approach to Model Heterogeneous MPSoC at Cycle Level",
    Proceedings of 11th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2008), 2008, Sept. 2-5, Parma, Italy. 
    

23. G.Palermo, C. Silvano e V. Zaccaria, "An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods",
    SAMOS VIII: International Symposium on Systems, Architectures, MOdeling and Simulation, Samos, Greece, July 21-24, 2008.
    

24. G.Palermo, C. Silvano e V. Zaccaria, "An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints",
    IEEE Symposium on Application Specific Processors (SASP 2008), Co-located with DAC 2008, 8-9 June 2008, Anaheim (CA - USA), pp.75-82.
    

25. M. Sykora, G. Agosta e C. Silvano, “Dynamic Configuration of ApplicationSpecific Implicit Instructions for Embedded Pipelined Processors”,
    SAC2008: 23rd Annual ACM Symposium on Applied Computing, Fortaleza, Brazil, 16-20 marzo, 2008. BEST PAPER AWARD SAC2008 - Applications Theme.

26. G. Palermo, G. Mariani, C. Silvano, R. Locatelli, M. Coppola, "A Topology Design Customization Approach for STNoC",
    In Proceedings of NanoNets'07 - International Conference on NanoNetworks. Catania, Italy, September 2007.

27. L. Fiorin, G. Palermo, S. Lukovic, C. Silvano, "A Data Protection Unit for NoC-based Architectures",
    CODES+ISSS '07: Proceedings of the 5th IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis, Salzburg, Austria, 2007, pp. 167--172.

28. G. Palermo, G. Mariani, C. Silvano, R. Locatelli, M. Coppola, "Application-Specific Topology Design Customization for STNoC",
    Proceedings of 10th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007),  2007, Lübeck, Germany, pp. 547-550.  

29. Leandro Fiorin, Cristina Silvano, Mariagiovanna Sami, "Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations",
    Proceedings of 10th IEEE Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007),  2007, Lübeck, Germany, pp. 539-542.

30. G. Palermo, G. Mariani, C. Silvano, R. Locatelli, M. Coppola, "Mapping and Topology Customization Approaches for Application-Specific STNoC Designs",
    In IEEE Proceedings of ASAP'07 - 18th International Conference on Application-specific Systems, Architectures and Processors. Montréal, Québec, Canada, July 2007, pp. 61-68.

31. G. Beltrame, D. Sciuto, C. Silvano, "Decision-theoretic Exploration of Multi-Processor Platforms",
    CODES-ISSS06, Proceedings of the 4th IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis,October 22-25, 2006, Seoul, Korea, pp. 205-210.

32. Beltrame G., Sciuto D., Silvano C., Paulin P., Bensoudane E., "An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures" 
    IFIP-VLSI-SOC 2006, 2006 IFIP International Conference on Very Large Scale Integration, Publication Date: 16-18 Oct. 2006 On page(s): 146-151 ISBN: 3-901882-19-7 

33. M. Monchiero, G. Palermo, C. Silvano, O. Villa, "Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors"
    IC-SAMOS VI Conference - Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos (Greece), July 17 - 20, 2006, pp. 144-151.

34. M. Monchiero, G. Palermo, C. Silvano, O. Villa, "Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs",
    DATE 2006: Design, Automation and Test in Europe, Conference and Exhibition, 6-10 March 2006, Munich, GERMANY, pp. 606-611.

35. G. Beltrame, D. Sciuto, C. Silvano, D. Lyonnard, C. Pilkington, "Exploiting TLM and Object Introspection for System-Level Simulation",
    DATE 2006: Design, Automation and Test in Europe Conference and Exhibition, 6-10 March 2006, Munich, GERMANY, pp. 100-105.

36.  M. Monchiero, G. Palermo, C. Silvano, O. Villa, “An Efficient Synchronization Technique for Multiprocessor Systems on-Chip”,
    ACM SIGARCH Computer Architecture News, Vol. 34, Issue1, March 2006, pp. 33-40, Special Issue on: MEDEA '05: Proc. of the 2005 workshop on MEmory performance (IEEE Computer Society Publisher), Saint Louis, Missouri, September 17 - 21, 2005.

37. G. Beltrame, G. Palermo, D. Sciuto, C. Silvano, “Plug-in of Power Models in the StepNP  Exploration Platform: Analysis of Power/Performance Trade-offs”,
    CASES 2004 - International ACM Conference on Compilers, Architectures and  Synthesis for Embedded Systems, Washington DC, USA, 22-25 September, 2004,  pp. 85-92, ISBN:1-58113-890-3.

38. G. Palermo, C. Silvano, “PIRATE: A Framework for Power/Performance Exploration of Network-On-Chip Architectures”, 
    Proc. of  PATMOS 2004: 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Greece, 15-17 September, 2004, 
    Lecture Notes in Computer Science, Springer, Vol. 3254, 2004, ISBN 978-3-540-23095-3, pp. 521-531.

39. M. Monchiero, G. Palermo, M. Sami, C. Silvano, V. Zaccaria, and R. Zafalon, "Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors",
    GLS-VLSI'04: Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26--28, 2004, Boston, MA, USA, pp. 440-443.

40. G.Agosta, G. Palermo, C. Silvano, “Multi-Objective Co-Exploration of Source Code Transformations and Design Space Architecture for Low-Power Embedded Systems”.
    In SAC04: Proceedings of the 2004 ACM Symposium on Applied Computing, 14-17 March 2004, Nicosia, Cyprus, pp. 891-896, ISBN:1-58113-812-1.

41. G. Palermo, C. Silvano, V. Zaccaria, ”A Flexible Framework for Fast Multi-Objective Design Space Exploration of Embedded Systems” 
    Proc. of PATMOS 2003: 13th International Workshop on Power and Timing Modeling, Optimization and Simulation,  September 10-12, 2003, Torino, Italy, Lecture Notes in Computer Science, Springer, Volume 2799, 2003, ISBN: 978-3-540-20074-1, pp. pp. 249 – 258.

42. G. Palermo, M. Sami, C. Silvano, V. Zaccaria, R. Zafalon, ”Branch Prediction Techniques for Low-Power VLIW Processors”
    GLS-VLSI'03: Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 28--29, 2003, Washington, DC, USA, pp. 225-228, ISBN:1-58113-677-3.

43. G. Palermo, C. Silvano, S. Valsecchi, V. Zaccaria, ”A System-Level Methodology for Fast Multi-Objective Design Space Exploration”
    GLS-VLSI'03: Proceedings of the April 28--29, 2003, Washington, DC, USA, pp. 92-95, ISBN:1-58113-677-3.

44. L. Salvemini, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon,
    ”A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems”  
    SAC03: Proceedings of the 2003 ACM Symposium on Applied Computing, 9-12 March 2003, Melbourne, Florida, USA, pp. 672-678, ISBN:1-58113-624-2

45. G. Palermo, C. Silvano, V. Zaccaria, ”Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture”, DATE 2003: Design, Automation and Test in Europe, Conference and Exhibition, 03–07 Marzo 2003, Munich, GERMANY, Pages: 182-187 suppl.

46. A. Bona, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, "Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering"
    DAC2002 - ACM/IEEE Design Automation Conference, 10-14 giugno, 2002, New Orleans, USA, Pages: 886-891. 
    Preliminary version on:

47. L. Benini, D. Bruni, M. Chinosi, C. Silvano, V. Zaccaria, and R. Zafalon, “A Power Modeling and Estimation Framework for VLIW-based Embedded Systems”, 
    PATMOS01- IEEE Eleventh International Workshop on Power and Timing Modeling, Optimization and Simulation, Sept. 26-28, 2001, Yverdon-les-Bains, Switzerland.
    This paper has been selected to be re-published on: ST Journal of System Research, No. 0, July 2003, Art. 5, pp. 52-60.

48. W. Fornaciari, D. Sciuto, C. Silvano, V. Zaccaria, “Fast System-Level Exploration of Memory Architectures Driven by Energy-Delay Metrics”, 
    ISCAS2001: IEEE Int. Symposium on Circuits and Systems, Sydney, Australia, May 5-7, 2001, pp.502-505, vol.4.

49. W. Fornaciari, D. Sciuto, C. Silvano, V. Zaccaria, “A Design Framework to Efficiently Explore Energy-Delay Tradeoffs”, CODES-2001: 9th ACM/IEEE International Symposium on Hardware/Software Co-Design (Former Workshop), Copenhagen (Danmark), Apr. 25-27, 2001, pp. 260-265.

50. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, “ Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors”,  
    DATE2001: IEEE Design, Automation and Test Conference in Europe, Munich, Germany, Mar. 13-16, 2001, pp. 252-257.

51. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, “Power Exploration for Embedded VLIW Architectures”,  
    ICCAD-2000: IEEE/ACM Int. Conference on Computer Aided Design, San Jose, CA, Nov. 5-9, 2000, pp. 498-503.

52. P. Bacchetta, L. Daldoss, D. Sciuto, C. Silvano, “Low-Power State Assignment Techniques for Finite State Machines”, ISCAS2000: IEEE Int. Symposium on Circuits and Systems, Geneva (Swizerland), May 28-31, 2000, pp. 641-644, Vol. 2.

53. M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, “Instruction-Level Power Estimation for Embedded VLIW Cores”,  
    CODES-2000: 8th ACM/IEEE International Workshop on Hardware/Software Co-Design, San Diego, CA, May 3-5, 2000, pp. 34-38.

54. W. Fornaciari, M. Polentarutti, D. Sciuto, C. Silvano, “Power Optimization of System-Level Address Buses based on Software Profiling”, 
    CODES-2000: 8th ACM/IEEE International Workshop on Hardware/Software Co-Design, San Diego, CA, May 3-5, 2000, pp. 29-33.

55. W. Fornaciari, D. Sciuto, C. Silvano, “Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study”, 
    ICCD-99: 1999 IEEE International  Conference  on Computer Design, Austin, TX (USA), Oct. 10-13, 1999, pp. 131-136.

56. W. Fornaciari, D. Sciuto, C. Silvano, “Power Estimation for Architectural Exploration of HW/SW Communication on System-Level Buses”, 
    CODES-99: ACM/IEEE 7th International Workshop on Hardware/Software Co-Design, Rome, Italy, 3-5 maggio, 1999, pp. 152-156.

57. W. Fornaciari, D. Sciuto, C. Silvano, “Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems”, 
    DATE-99: IEEE Design, Automation and Test in Europe, Conference and Exhibition 1999, Munich (Germany), Mar. 9-12, 1999, pp. 762-763.

58. C. Guardiani, A. Macii, E. Macii, M. Poncino, M. Rossello, R. Scarsi, C. Silvano, R. Zafalon, “RTL Power Embedded Estimation in a Industrial Design Flow”,  
    IEEE Alessandro Volta Memorial Workshop on Low-Power Design, Como, Italy, Mar. 4-5, 1999, pp. 91-96.

59. D. Sciuto, C. Silvano, R. Stefanelli, “Systematic AUED Codes for Self-Checking Architectures”, 
    DFT-98: 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Austin, TX (USA), Nov. 2-4, 1998, pp. 183-191.

60. N. Dragone, C. Guardiani, C. Silvano, R. Zafalon, “Power Invariant Vector Compaction based on Bit Clustering and Temporal Partitioning”, 
    ISLPED98: 1998 IEEE International Symposium on Low-Power Electronics and Design, Monterey, CA (USA), Aug. 1998, pp. 118-120.

61. L. Daldoss, D. Sciuto, C. Silvano, “State Encoding for Low Power Embedded Controllers”,  
    ISCAS-98: IEEE International Symposium on Circuits and Systems, Monterey, CA (USA), May 31 – Jun. 3, 1998, pp. 421-424, Vol. 2. 

62. L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Address Bus Encoding Techniques for System-Level Power Optimization”,
    DATE-98: IEEE Design, Automation and Test in Europe, Conference an Exhibition 1998, Paris (F), Feb. 23-26, 1998, pp. 861-866.
    This paper has been selected to be re-published on:  
    Design, Automation, and Test in Europe - The Most Influential Papers of 10 Years DATE Lauwereins, Rudy; Madsen, Jan (Eds.), 2008, Approx. 250 p., ISBN: 978-1-4020-6487-6, Springer Ed.

63. W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano, “System-level Power Evaluation Metrics”, 
    ISIS-97: Second Annual IEEE International Conference on Innovative Systems in Silicon, Austin, TX (USA), Oct. 8-10, 1997, pp. 323-330.

64. W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano, “High-Level Power Estimation of VLSI Systems”,  
    ISCAS-97: IEEE International Symposium on Circuits and Systems, Hong Kong, Jun. 9-12, 1997, pp. 1804-1807, Vol.3.

65. L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, “Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems”, GLS-VLSI-97: Proceedings of the 7Urbana, IL (USA), Mar. 13-15, 1997, pp. 77-82.

66. W. Fornaciari, P. Gubian, D. Sciuto, C. Silvano, “A Conceptual Analysis Framework for Low Power Design of Embedded Systems”,  
    ISIS-96: Eighth Annual IEEE International Conference on Innovative Systems in Silicon (Previously: International Conference on Wafer Scale Integration), Austin, TX (USA), Oct. 9-11, 1996, pp. 170-179.

67. L. Penzo, D. Sciuto, C. Silvano, “GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications”, 
    ISCAS-95: IEEE International Symposium on Circuits and Systems, Seattle, WA (USA), Apr. 29 – May 3, 1995, pp. 912-915.

68. L. Penzo, D. Sciuto, C. Silvano, “VLSI Design of Systematic Odd-Weight-Column Byte Error Detecting SEC-DED Codes”, 
    VLSI-95: IEEE 8th International Conference on VLSI Design, New Delhi (India), Jan. 4-7, 1995, pp. 156-160.

69. L. Populin, G. Sada, C. Silvano, “RamGen: a Dual Port Static RAM Generator”, ASIC-92: Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit, Rochester, NY (USA), 21-25 settembre, 1992, pp. 509-512

70. F. Bozzetti, C. Silvano, "Architecture and Design Methodology of a 32-bit Microprocessor”, Proc. of COMPEURO-91: Advanced Computer Technology, Reliable Systems and Applications, 5th Annual European Computer Conference Bologna (Italy), 13-16 maggio, 1991, pp. 613-617.

International Workshops with Informal Proceedings and Invited Papers 

1. C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Huebert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers H. Meyr, J. Ansari, P. Mahonen, and B. Vanthournout " Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: The 2PARMA Approach ", INDIN 2011: IEEE International Conference on Industrial Informatics, pp. XX-XX, Portugal, Lisbon, July 2011. Invited Paper

2. C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Huebert, B. Stabernack, J. Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers H. Meyr, J. Ansari, P. Mahonen, and B. Vanthournout " Parallel Programming and Run-time Resource Management Framework for Many-core Platfomrs: The 2PARMA Approach ", ReCoSoc 2011: International Workshop on Reconfigurable Communication-centric System on-Chip, pp. XX-XX, Montpellier, France, June 2011. Invited Paper

3. Cristina Silvano, Gianluca Palermo, Vittorio Zaccaria, William Fornaciari, Roberto Zafalon, Sara Bocchio, Marcos Martinez, Marise Wouters, Gert Vanmeerbeeck, Prabhat Avasare, Luca Onesti, Carlos Kavka, Umberto Bondi, Giovanni Mariani, Eugenio Villar, Hector Posadas, Chris Y. Q. Wu, Fan Dongrui, and Zhang Hao. " MULTICUBE: Multi-Objective Design Space Exploration of Multiprocessor Architectures for Embedded Multimedia Applications ", In First Friday Workshop on "Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications", co-located with DATE09. Nice, France, April 2009.

4. Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. " Multicube Explorer - A Design Space Exploration Framework for Embedded Systems-on- Chip " , In First Friday Workshop on "Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications", co-located with DATE09. Nice, France, April 2009.

5. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. "A doe/rsm-based strategy for an efficient design space exploration targeted to CMPs. " In RAPIDO 2009: Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Co-located with HiPEAC Conference 2009, Paphos, Cyprus, January 2009.

6. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa. "An Efficient Synchronization Technique for Multiprocessor Systems on-Chip". IN MEDEA-05 - International Workshop on MEmory performance: DEaling with Applications, systems and architecture". Saint Louis, Missouri. 17 September, 2005.

Ph. D. Thesis

1. “Power Estimation and Optimization Methodologies for Digital Circuits and Systems”,  
   Ph. D. Thesis in Information Engineering, Università degli Studi di Brescia.