International Patents

1. (in collaboration with G. Sada)
   European Patent Number EP 0 578 900, Application Number 92830383.3 titled: “Integrated CMOS static RAM”.
   Patent submitted: 16/07/1992. Patent granted: 5/11/1997.
   Patent's owner:  Bull HN Information Systems Italia.

2. European Patent Specification EP 0 629 051 B1, Application Number 93830254.4 titled: “Digital information error correcting apparatus for correcting single errors (SEC), detecting double errors (DED) and single byte multiple errors (SBD) and the correction of an odd number of single byte errors (ODD SBC)”.
   Patent submitted: 10/06/1993. Patent granted: 1/04/1998.
   Patent's owner: Bull HN Information Systems Italia.

3. USA Dept. of Commerce, Patent and Trademark Office, USA Patent Number 5535227, Patent Application Number 08/248140 titled: “Digital information error correcting apparatus for single error correcting (SEC), double error detecting (DED), single byte error detecting (SBED), and odd numbered single byte error correcting (OSBEC)”.
   Patent submitted: 23/05/1994. Patent granted: 9/07/1996.
   Patent's owner:  Bull HN Information Systems Italia.
   Extension of the European Patent [2].

4. (in collaboration with W. Fornciari, D. Sciuto, R. Zafalon, and D. Pau)
   European Patent Application Number 00830322.4-2212 titled: "Encoder/decoder architecture and related processing system".
   Patent submitted: 28/04/2000. Date of publication 31/10/2001.
   Patent's owner: STMicroelectronics.

5. (in collaboration with W. Fornciari, D. Sciuto, R. Zafalon, and D. Pau)
   USA Dept. of Commerce, Patent and Trademark Office, USA Patent Application Number 09/843533  titled: "Encoder/decoder architecture and related processing system".
   Patent submitted: 25/04/2001. Patent US 2002 0019896 A1. Date of publication 14/02/2002.
   Patent's owner: STMicroelectronics.
   Extension of the European Patent [4].

6. (in collaboration with M. Sami, D. Sciuto, V. Zaccaria, D. Pau, and R. Zafalon)
   European Patent Application Number 00830673.0-2201 titled: "Processor Architecture with variable stage pipeline".
   Patent submitted: 17/10/2000. Patent EP1 1996 29 A1 Date of publication 24/04/2002.
   Patent's owner: STMicroelectronics. 

7. USA Dept. of Commerce, Patent and Trademark Office, USA Patent Application Number 09/976241 titled: "Processor Architecture".
   Patent submitted: 11/10/2001. Patent US 6 889 317 granted on 03/05/2005.
   Patent's owner: STMicroelectronics.
   Extension of the European Patent [6].

8. (in collaboration with G. Palermo, L. Fiorin, V. Catalano, M. Coppola, R. Locatelli)
   European Patent Application Number 07301411.0-2413, Title: "Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit".
   Patent submitted: 28/09/2007. Patent under evaluation.
   Patent's owner: STMicroelectronics (Grenoble) SAS

9. (in collaboration with G. Palermo, L. Fiorin, V. Catalano, M. Coppola, R. Locatelli)
   USA Patent Application Number 361170-1112, Title: "Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit".
   Patent submitted: June 2008. Patent under evaluation.
   Patent's owner: STMicroelectronics (Grenoble) SAS
   Extension of the European Patent [8].